Sciweavers

TCAD
2010
112views more  TCAD 2010»
12 years 11 months ago
Multilayer Global Routing With Via and Wire Capacity Considerations
Global routing for modern large-scale circuit designs has attracted much attention in the recent literature. Most of the state-of-the-art academic global routers just work on a sim...
Chin-Hsiung Hsu, Huang-Yu Chen, Yao-Wen Chang
TCAD
2010
150views more  TCAD 2010»
12 years 11 months ago
Voltage and Temperature Aware Statistical Leakage Analysis Framework Using Artificial Neural Networks
Artificial neural networks (ANNs) have shown great promise in modeling circuit parameters for computer aided design applications. Leakage currents, which depend on process paramete...
Janakiraman Viraraghavan, Bharadwaj Amrutur, V. Vi...
TCAD
2010
133views more  TCAD 2010»
12 years 11 months ago
Defect-Tolerant Design and Optimization of a Digital Microfluidic Biochip for Protein Crystallization
Protein crystallization is a commonly used technique for protein analysis and subsequent drug design. It predicts the 3-D arrangement of the constituent amino acids, which in turn ...
Tao Xu, Krishnendu Chakrabarty, Vamsee K. Pamula
TCAD
2010
103views more  TCAD 2010»
12 years 11 months ago
Supervised Learning Based Power Management for Multicore Processors
- This paper presents a supervised learning based power management framework for a multi-processor system, where a power manager (PM) learns to predict the system performance state...
Hwisung Jung, Massoud Pedram
TCAD
2010
135views more  TCAD 2010»
12 years 11 months ago
DeFer: Deferred Decision Making Enabled Fixed-Outline Floorplanning Algorithm
In this paper, we present DeFer--a fast, high-quality, scalable, and nonstochastic fixed-outline floorplanning algorithm. DeFer generates a nonslicing floorplan by compacting a sli...
Jackey Z. Yan, Chris Chu
TCAD
2010
105views more  TCAD 2010»
12 years 11 months ago
Fault Tolerant Network on Chip Switching With Graceful Performance Degradation
The structural redundancy inherent to on-chip interconnection networks [networks on chip (NoC)] can be exploited by adaptive routing algorithms in order to provide connectivity eve...
Adán Kohler, Gert Schley, Martin Radetzki
TCAD
2010
94views more  TCAD 2010»
12 years 11 months ago
An Efficient Projector-Based Passivity Test for Descriptor Systems
Abstract--An efficient passivity test based on canonical projector techniques is proposed for descriptor systems (DSs) widely encountered in circuit and system modeling. The test f...
Zheng Zhang, Ngai Wong
TCAD
2010
130views more  TCAD 2010»
12 years 11 months ago
On ATPG for Multiple Aggressor Crosstalk Faults
Crosstalk faults have emerged as a significant mechanism for circuit failure. Long signal nets are of particular concern because they tend to have a higher coupling capacitance to...
Kunal P. Ganeshpure, Sandip Kundu
TCAD
2010
97views more  TCAD 2010»
12 years 11 months ago
Technology Mapping and Clustering for FPGA Architectures With Dual Supply Voltages
Abstract--This paper presents a technology mapping algorithm for field-programmable gate array architectures with dual supply voltages (Vdds) for power optimization. This is done w...
Deming Chen, Jason Cong, Chen Dong, Lei He, Fei Li...
TCAD
2010
106views more  TCAD 2010»
13 years 2 months ago
Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies
—With the scaling of complementary metal–oxide– semiconductor (CMOS) technology into the nanometer regime, the overshooting effect due to the input-to-output coupling capacit...
Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimo...