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TC
2002
9 years 11 months ago
Test Bus Sizing for System-on-a-Chip
Vikram Iyengar, Krishnendu Chakrabarty
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
10 years 3 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
ITC
1997
IEEE
123views Hardware» more  ITC 1997»
10 years 3 months ago
Modifying User-Defined Logic for Test Access to Embedded Cores
Testing embedded cores is a challenge because access to core I/Os is limited. The user-defined logic (ZJDL) surrounding the core may restrict the set of test vectors that can be a...
Bahram Pouya, Nur A. Touba
ITC
2000
IEEE
124views Hardware» more  ITC 2000»
10 years 4 months ago
Wrapper design for embedded core test
A wrapper is a thin shell around the core, that provides the switching between functional, and core-internal and core-external test modes. Together with a test access mechanism (T...
Yervant Zorian, Erik Jan Marinissen, Maurice Lousb...
DATE
2002
IEEE
89views Hardware» more  DATE 2002»
10 years 4 months ago
A Hierarchical Test Scheme for System-On-Chip Designs
System-on-chip (SOC) design methodology is becoming the trend in the IC industry. Integrating reusable cores from multiple sources is essential in SOC design, and different design...
Jin-Fu Li, Hsin-Jung Huang, Jeng-Bin Chen, Chih-Pi...
ATS
2002
IEEE
136views Hardware» more  ATS 2002»
10 years 4 months ago
Recent Advances in Test Planning for Modular Testing of Core-Based SOCs
Test planning for core-based system-on-a-chip (SOC) designs is necessary to reduce testing time and test cost. In this paper, we survey recent advances in test planning that addre...
Vikram Iyengar, Krishnendu Chakrabarty, Erik Jan M...
DATE
2003
IEEE
96views Hardware» more  DATE 2003»
10 years 5 months ago
Time Domain Multiplexed TAM: Implementation and Comparison
One of the dif´Čücult problems which core-based systemon-chip (SoC) designs face is test access. For testing the cores in a SoC, a special mechanism is required, since they are no...
Zahra Sadat Ebadi, André Ivanov
DATE
2006
IEEE
94views Hardware» more  DATE 2006»
10 years 5 months ago
Reuse-based test access and integrated test scheduling for network-on-chip
In this paper, we propose a new method for test access and test scheduling in NoC-based system. It relies on a progressive reuse of the network resources for transporting test dat...
Chunsheng Liu, Zach Link, Dhiraj K. Pradhan
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