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DSD
2005
IEEE
116views Hardware» more  DSD 2005»
13 years 10 months ago
Optimization of a Bus-based Test Data Transportation Mechanism in System-on-Chip
The increasing amount of test data needed to test SOC (System-on-Chip) entails efficient design of the TAM (test access mechanism), which is used to transport test data inside the...
Anders Larsson, Erik Larsson, Petru Eles, Zebo Pen...
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
14 years 4 months ago
A Novel Method to Improve the Test Efficiency of VLSI Tests
This paper considers reducing the cost of test application by permuting test vectors to improve their defect coverage. Algorithms for test reordering are developed with the goal o...
Hailong Cui, Sharad C. Seth, Shashank K. Mehta