AAAI
1994
13 years 5 months ago
1994
We present a formal theory of model-based testing, an algorithm for test generation based on it, and outline how testing is implemented by a diagnostic engine. The key to making t...
PTS
2000
13 years 5 months ago
2000
We discuss a case study of automatic test generation and test execution based on formal methods. The case is the Conference Protocol, a simple, chatbox-like protocol, for which (fo...
SDL
2001
13 years 5 months ago
2001
The purpose of this paper is to describe how computer-aided test generation methods can benefit from the time features and extensions to MSC, SDL and TTCN which are either already ...
EVOW
2008
Springer
13 years 6 months ago
2008
Springer
Traditional test generation methodologies for peripheral cores are performed by a skilled test engineer, leading to long generation times. In this paper a test generation methodolo...
ATAL
2008
Springer
13 years 6 months ago
2008
Springer
This paper investigates software agents testing, and in particular how to automate test generation. We propose a novel approach, which takes advantage of agent interaction ontolog...
CAV
2010
Springer
13 years 6 months ago
2010
Springer
Abstract. We describe an interpolant-based approach to test generation and model checking for sequential programs. The method generates Floyd/Hoare style annotations of the program...
ASPDAC
2006
ACM
13 years 8 months ago
2006
ACM
The verification of modern computing systems has grown to dominate the cost of system design, often with limited success as designs continue to be released with latent bugs. This t...
ITC
1989
IEEE
13 years 8 months ago
1989
IEEE
: The concept of a pseudo-exhaustive test for sequential circuits is introduced in a similar way as it is used for combinational networks. Instead of test sets one has to apply pse...
VTS
1996
IEEE
13 years 8 months ago
1996
IEEE
A fault-oriented sequential circuit test generator is described in which various types of distinguishing sequences are derived, both statically and dynamically, to aid the test ge...
ICCAD
1996
IEEE
13 years 8 months ago
1996
IEEE
State justification is a time-consuming operation in test generation for sequential circuits. In this paper, we present a technique to rapidly identify state elements (flip-flops)...