Sciweavers

VTS
2005
IEEE
106views Hardware» more  VTS 2005»
13 years 10 months ago
Segmented Addressable Scan Architecture
This paper presents a test architecture that addresses multiple problems faced in digital IC testing. These problems are test data volume, test application time, test power consum...
Ahmad A. Al-Yamani, Erik Chmelar, Mikhail Grinchuc...