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ATS
2009
IEEE
117views Hardware» more  ATS 2009»
13 years 11 months ago
N-distinguishing Tests for Enhanced Defect Diagnosis
Diagnostic ATPG has traditionally been used to generate test patterns that distinguish pairs of modeled faults. In this work, we investigate the use of n-distinguishing test sets,...
Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith...
ICCAD
2001
IEEE
84views Hardware» more  ICCAD 2001»
14 years 1 months ago
On Identifying Don't Care Inputs of Test Patterns for Combinational Circuits
Given a test set for stuck-at faults, some of primary input values may be changed to opposite logic values without losing fault coverage. We can regard such input values as don’...
Seiji Kajihara, Kohei Miyase
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
14 years 4 months ago
A Partitioning and Storage Based Built-In Test Pattern Generation Method for Scan Circuits
We describe a built-in test pattern generation method for scan circuits. The method is based on partitioning and storage of test sets. Under this method, a precomputed test set is...
Irith Pomeranz, Sudhakar M. Reddy