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JCPHY
2011
109views more  JCPHY 2011»
9 years 7 months ago
Fast construction of hierarchical matrix representation from matrix-vector multiplication
We develop a hierarchical matrix construction algorithm using matrixvector multiplications, based on the randomized singular value decomposition of low-rank matrices. The algorith...
Lin Lin, Jianfeng Lu, Lexing Ying
TIT
2010
174views Education» more  TIT 2010»
9 years 11 months ago
Toeplitz Compressed Sensing Matrices With Applications to Sparse Channel Estimation
Compressed sensing (CS) has recently emerged as a powerful signal acquisition paradigm. In essence, CS enables the recovery of high-dimensional sparse signals from relatively few ...
Jarvis Haupt, Waheed Uz Zaman Bajwa, Gil M. Raz, R...
ATS
2010
IEEE
250views Hardware» more  ATS 2010»
10 years 1 months ago
Efficient Embedding of Deterministic Test Data
Systems with many integrated circuits (ICs), often of the same type, are increasingly common to meet the constant performance demand. However, systems in recent semiconductor techn...
Mudassar Majeed, Daniel Ahlstrom, Urban Ingelsson,...
ENGL
2007
180views more  ENGL 2007»
10 years 4 months ago
Reordering Algorithm for Minimizing Test Power in VLSI Circuits
— Power consumption has become a crucial concern in Built In Self Test (BIST) due to the switching activity in the circuit under test(CUT). In this paper we present a novel metho...
K. Paramasivam, K. Gunavathi
EAAI
2007
103views more  EAAI 2007»
10 years 4 months ago
Particle swarm-based optimal partitioning algorithm for combinational CMOS circuits
This paper presents a swarm intelligence based approach to optimally partition combinational CMOS circuits for pseudoexhaustive testing. The partitioning algorithm ensures reducti...
Ganesh K. Venayagamoorthy, Scott C. Smith, Gaurav ...
FPGA
2000
ACM
114views FPGA» more  FPGA 2000»
10 years 8 months ago
Generating highly-routable sparse crossbars for PLDs
A method for evaluating and constructing sparse crossbars which are both area efficient and highly routable is presented. The evaluation method uses a network flow algorithm to ac...
Guy G. Lemieux, Paul Leventis, David M. Lewis
VLSID
1993
IEEE
136views VLSI» more  VLSID 1993»
10 years 8 months ago
A Simulation-Based Test Generation Scheme Using Genetic Algorithms
This paper discusses a Genetic Algorithm-based method of generating test vectorsfor detecting faults in combinational circuits. The GA-based approach combines the merits of two te...
M. Srinivas, Lalit M. Patnaik
DAC
1997
ACM
10 years 8 months ago
Toward Formalizing a Validation Methodology Using Simulation Coverage
The biggest obstacle in the formal verification of large designs is their very large state spaces, which cannot be handled even by techniques such as implicit state space travers...
Aarti Gupta, Sharad Malik, Pranav Ashar
DFT
2002
IEEE
128views VLSI» more  DFT 2002»
10 years 9 months ago
Matrix-Based Test Vector Decompression Using an Embedded Processor
This paper describes a new compression/decompression methodology for using an embedded processor to test the other components of a system-on-a-chip (SoC). The deterministic test v...
Kedarnath J. Balakrishnan, Nur A. Touba
ITC
2003
IEEE
120views Hardware» more  ITC 2003»
10 years 9 months ago
Test Vector Generation Based on Correlation Model for Ratio-Iddq
For ratio-Iddq testing, the test performance is significantly affected by the correlation between two currents of different input patterns as process parameters vary. In this p...
Xiaoyun Sun, Larry L. Kinney, Bapiraju Vinnakota
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