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CF
2011
ACM
10 years 5 months ago
Hybrid high-performance low-power and ultra-low energy reliable caches
Ubiquitous computing has become a very popular paradigm. The most suitable technological solution for those systems consists of using hybrid processors able to operate at high vol...
Bojan Maric, Jaume Abella, Francisco J. Cazorla, M...
JCSC
2002
129views more  JCSC 2002»
11 years 5 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
TVLSI
2008
197views more  TVLSI 2008»
11 years 5 months ago
Leakage Minimization of SRAM Cells in a Dual-Vt and Dual-Tox Technology
-- Aggressive CMOS scaling results in low threshold voltage and thin oxide thickness for transistors manufactured in deep submicron regime. As a result, reducing the subthreshold a...
Behnam Amelifard, Farzan Fallah, Massoud Pedram
DT
2006
109views more  DT 2006»
11 years 5 months ago
Test Consideration for Nanometer-Scale CMOS Circuits
The ITRS (International Technology Roadmap for Semiconductors) predicts aggressive scaling down of device size, transistor threshold voltage and oxide thickness to meet growing de...
Kaushik Roy, T. M. Mak, Kwang-Ting (Tim) Cheng
DELTA
2008
IEEE
11 years 7 months ago
Threshold Voltage Start-up Boost Converter for Sub-mA Applications
A threshold voltage start-up (TVS) scheme for a boost converter is presented. The TVS converter could start up at the average threshold voltage of the fabrication process, and con...
Ngok-Man Sze, Wing-Hung Ki, Chi-Ying Tsui
ISCAS
1995
IEEE
107views Hardware» more  ISCAS 1995»
11 years 9 months ago
Power Dissipation in Deep Submicron CMOS Digital Circuits
— This paper introduces a simple analytical model for estimating standby and switching power dissipation in deep submicron CMOS digital circuits. The model is based on Berkeley S...
R. X. Gu, Mohamed I. Elmasry
EURODAC
1995
IEEE
182views VHDL» more  EURODAC 1995»
11 years 9 months ago
Delay modelling improvement for low voltage applications
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
Jean Michel Daga, Michel Robert, Daniel Auvergne
ITC
2003
IEEE
122views Hardware» more  ITC 2003»
11 years 10 months ago
EEPROM Memory: Threshold Voltage Built In Self Diagnosis
Knowing, that the threshold voltage of the EEPROM memory cells is a key parameter to determine the overall performance of the memory, a build in structure to extract this informat...
Jean Michel Portal, Hassen Aziza, Didier Né...
SBCCI
2005
ACM
111views VLSI» more  SBCCI 2005»
11 years 11 months ago
Total leakage power optimization with improved mixed gates
Gate oxide tunneling current Igate and sub-threshold current Isub dominate the leakage of designs. The latter depends on threshold voltage Vth while Igate vary with the thickness ...
Frank Sill, Frank Grassert, Dirk Timmermann
MTDT
2006
IEEE
154views Hardware» more  MTDT 2006»
11 years 11 months ago
SRAM Cell Current in Low Leakage Design
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, C...
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