EUROPAR
2011
Springer
12 years 4 months ago
2011
Springer
DOALL loops are tiled to exploit DOALL parallelism and data locality on GPUs. In contrast, due to loop-carried dependences, DOACROSS loops must be skewed first in order to make ti...
PCI
2005
Springer
13 years 10 months ago
2005
Springer
Cache misses form a major bottleneck for memory-intensive applications, due to the significant latency of main memory accesses. Loop tiling, in conjunction with other program tran...
CF
2006
ACM
13 years 10 months ago
2006
ACM
In this paper, we investigate the power implications of tile size selection for tile-based processors. We refer to this investigation as a tile granularity study. This is accompli...