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ASYNC
1997
IEEE
103views Hardware» more  ASYNC 1997»
9 years 9 months ago
Efficient Timing Analysis Algorithms for Timed State Space Exploration
This paper presents new timing analysis algorithms for efficient state space exploration during timed circuit synthesis. Timed circuits are a class of asynchronous circuits that i...
Wendy Belluomini, Chris J. Myers
ATS
2001
IEEE
101views Hardware» more  ATS 2001»
9 years 9 months ago
Framework of Timed Trace Theoretic Verification Revisited
This paper develops a framework to support trace theoretic verification of timed circuits and systems. A theoretical foundation for classifying timed traces as either successes or...
Bin Zhou, Tomohiro Yoneda, Chris J. Myers
VLSID
1999
IEEE
91views VLSI» more  VLSID 1999»
9 years 10 months ago
Timed Circuit Synthesis Using Implicit Methods
The design and synthesis of asynchronous circuits is gaining importance in both the industrial and academic worlds. Timed circuits are a class of asynchronous circuits that incorp...
Robert Thacker, Wendy Belluomini, Chris J. Myers
ATVA
2004
Springer
78views Hardware» more  ATVA 2004»
9 years 11 months ago
Partial Order Reduction for Detecting Safety and Timing Failures of Timed Circuits
This paper proposes a partial order reduction algorithm for timed trace theoretic verification in order to detect both safety failures and timing failures of timed circuits effic...
Denduang Pradubsuwun, Tomohiro Yoneda, Chris J. My...
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