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ICCAD
1997
IEEE
122views Hardware» more  ICCAD 1997»
13 years 8 months ago
Approximate timing analysis of combinational circuits under the XBD0 model
This paper is concerned with approximate delay computation algorithms for combinational circuits. As a result of intensive research in the early 90’s [3, 8] efficient tools exi...
Yuji Kukimoto, Wilsin Gosti, Alexander Saldanha, R...
LCTRTS
1998
Springer
13 years 8 months ago
Integrating Path and Timing Analysis Using Instruction-Level Simulation Techniques
Abstract. Previously published methods for estimation of the worstcase execution time on contemporary processors with complex pipelines and multi-level memory hierarchies result in...
Thomas Lundqvist, Per Stenström
ICCAD
1998
IEEE
98views Hardware» more  ICCAD 1998»
13 years 8 months ago
Determination of worst-case aggressor alignment for delay calculation
Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic...
Paul D. Gross, Ravishankar Arunachalam, Karthik Ra...
DATE
1998
IEEE
98views Hardware» more  DATE 1998»
13 years 8 months ago
AFTA: A Formal Delay Model for Functional Timing Analysis
Despite its importance, we find that a rigorous theoretical foundation for performing timing analysis has been lacking so far. As a result, we have initiated a research project th...
V. Chandramouli, Jesse Whittemore, Karem A. Sakall...
DATE
2000
IEEE
113views Hardware» more  DATE 2000»
13 years 8 months ago
Static Timing Analysis of Embedded Software on Advanced Processor Architectures
This paper examines several techniques for static timing analysis. In detail, the first part of the paper analyzes the connection of prediction accuracy (worst case execution tim...
André Hergenhan, Wolfgang Rosenstiel
DATE
2010
IEEE
161views Hardware» more  DATE 2010»
13 years 9 months ago
Aging-resilient design of pipelined architectures using novel detection and correction circuits
—Time-dependent performance degradation due to transistor aging caused by mechanisms such as Negative Bias Temperature Instability (NBTI) and Hot Carrier Injection (HCI) is one o...
Hamed F. Dadgour, Kaustav Banerjee
DATE
2003
IEEE
90views Hardware» more  DATE 2003»
13 years 9 months ago
Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching
While fast timing analysis methods, such as asymptotic waveform evaluation (AWE), have been well established for linear circuits, the timing analysis for non-linear circuits, whic...
Zhong Wang, Jianwen Zhu
FPGA
2004
ACM
126views FPGA» more  FPGA 2004»
13 years 9 months ago
A synthesis oriented omniscient manual editor
The cost functions used to evaluate logic synthesis transformations for FPGAs are far removed from the final speed and routability determined after placement, routing and timing a...
Tomasz S. Czajkowski, Jonathan Rose
ICDCIT
2005
Springer
13 years 9 months ago
Analyzing Loop Paths for Execution Time Estimation
Abstract. Statically estimating the worst case execution time of a program is important for real-time embedded software. This is difficult even in the programming language level du...
Abhik Roychoudhury, Tulika Mitra, Hemendra Singh N...
ASPDAC
2005
ACM
95views Hardware» more  ASPDAC 2005»
13 years 10 months ago
Timing analysis considering temporal supply voltage fluctuation
Abstract— This paper proposes an approach to cope with temporal power/ground voltage fluctuation for static timing analysis. The proposed approach replaces temporal noise with a...
Masanori Hashimoto, Junji Yamaguchi, Takashi Sato,...