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    ASPDAC
    1999
    ACM
    60views Hardware» more  ASPDAC 1999»
    Timing Optimization of Logic Network Using Gate Duplication
    13 years 9 months ago
    Timing Optimization of Logic Network Using Gate Duplication
    Download  www.cecs.uci.edu
    We present a timing optimization algorithm based on the concept of gate duplication on the technologydecomposed network. We first examine the relationship between gate duplication...
    Chun-hong Chen, Chi-Ying Tsui
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