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VLSID
1993
IEEE
114views VLSI» more  VLSID 1993»
13 years 9 months ago
A Methodology for Generating Application Specific Tree Multipliers
Low latency, application, specific multipliers are required for m,any DSP algorithms. Tree multipliers are an obvious answer to this requirement. However, tree architectures have ...
S. Ramanathan, Nibedita Mohanty, V. Visvanathan
ARITH
2003
IEEE
13 years 10 months ago
High-Performance Left-to-Right Array Multiplier Design
We propose a split array multiplier organized in a left-to-right leapfrog (LRLF) structure with reduced delay compared to conventional array multipliers. Moreover, the proposed de...
Zhijun Huang, Milos D. Ercegovac