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    TVLSI
    2002
    93views more  TVLSI 2002»
    Simultaneous switching noise in on-chip CMOS power distribution networks
    13 years 4 months ago
    Simultaneous switching noise in on-chip CMOS power distribution networks
    Download  www.ece.rochester.edu
    Simultaneous switching noise (SSN) has become an important issue in the design of the internal on-chip power distribution networks in current very large scale integration/ultra lar...
    Kevin T. Tang, Eby G. Friedman
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    TVLSI
    2002
    130views more  TVLSI 2002»
    HW/SW codesign techniques for dynamically reconfigurable architectures
    13 years 4 months ago
    HW/SW codesign techniques for dynamically reconfigurable architectures
    Download  www.csie.ntu.edu.tw
    Abstract--Hardward/software (HW/SW) codesign and reconfigurable computing are commonly used methodologies for digitalsystems design. However, no previous work has been carried out ...
    Juanjo Noguera, Rosa M. Badia
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    TVLSI
    2002
    102views more  TVLSI 2002»
    Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
    13 years 4 months ago
    Algorithm level re-computing using implementation diversity: a register transfer level concurrent error detection technique
    Download  www.ece.uic.edu
    Concurrent error detection (CED) based on time redundancy entails performing the normal computation and the re-computation at different times and then comparing their results. Time...
    Ramesh Karri, Kaijie Wu
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    TVLSI
    2002
    102views more  TVLSI 2002»
    Power-optimal encoding for a DRAM address bus
    13 years 4 months ago
    Power-optimal encoding for a DRAM address bus
    Download  atrak.usc.edu
    This paper presents an irredundant encoding technique to minimize the switching activity on a multiplexed Dynamic RAM (DRAM) address bus. The DRAM switching activity can be classif...
    Wei-Chung Cheng, Massoud Pedram
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    TVLSI
    2002
    102views more  TVLSI 2002»
    Low-power data forwarding for VLIW embedded architectures
    13 years 4 months ago
    Low-power data forwarding for VLIW embedded architectures
    Download  home.dei.polimi.it
    In this paper, we propose a low-power approach to the design of embedded very long instruction word (VLIW) processor architectures based on the forwarding (or bypassing) hardware, ...
    Mariagiovanna Sami, Donatella Sciuto, Cristina Sil...
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    TVLSI
    2002
    91views more  TVLSI 2002»
    On the design of low-voltage, low-power CMOS analog multipliers for RF applications
    13 years 4 months ago
    On the design of low-voltage, low-power CMOS analog multipliers for RF applications
    Download  ims.unipv.it
    Carl James Debono, Franco Maloberti, Joseph Micall...
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    TVLSI
    2002
    121views more  TVLSI 2002»
    On-chip decoupling capacitor optimization using architectural level prediction
    13 years 4 months ago
    On-chip decoupling capacitor optimization using architectural level prediction
    Download  users.ece.gatech.edu
    Switching activity-generated power-supply grid-noise presents a major obstacle to the reduction of supply voltage in future generation semiconductor technologies. A popular techniq...
    Mondira Deb Pant, Pankaj Pant, D. Scott Wills
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