Sciweavers

TVLSI
2008
90views more  TVLSI 2008»
13 years 4 months ago
A Special-Purpose Architecture for Solving the Breakpoint Median Problem
Abstract--In this paper, we describe the design for a co-processor for whole-genome phylogenetic reconstruction. Our current design performs a parallelized breakpoint median comput...
Jason D. Bakos, Panormitis E. Elenis
TVLSI
2008
105views more  TVLSI 2008»
13 years 4 months ago
Fast Estimation of Timing Yield Bounds for Process Variations
With aggressive scaling down of feature sizes in VLSI fabrication, process variation has become a critical issue in designs. We show that two necessary conditions for the "Max...
Ruiming Chen, Hai Zhou
TVLSI
2008
120views more  TVLSI 2008»
13 years 4 months ago
An Interactive Design Environment for C-Based High-Level Synthesis of RTL Processors
Much effort in register transfer level (RTL) design has been devoted to developing "push-button" types of tools. However, given the highly complex nature, and lack of con...
Dongwan Shin, Andreas Gerstlauer, Rainer Döme...
TVLSI
2008
153views more  TVLSI 2008»
13 years 4 months ago
Characterization of a Novel Nine-Transistor SRAM Cell
Data stability of SRAM cells has become an important issue with the scaling of CMOS technology. Memory banks are also important sources of leakage since the majority of transistors...
Zhiyu Liu, Volkan Kursun
TVLSI
2008
78views more  TVLSI 2008»
13 years 4 months ago
Minimal-Power, Delay-Balanced Smart Repeaters for Global Interconnects in the Nanometer Regime
Abstract--A SMART repeater is proposed for driving capacitively-coupled, global-length on-chip interconnects that alters its drive strength dynamically to match the relative bit pa...
Roshan Weerasekera, Dinesh Pamunuwa, Li-Rong Zheng...
TVLSI
2008
164views more  TVLSI 2008»
13 years 4 months ago
Dynamically Configurable Bus Topologies for High-Performance On-Chip Communication
The on-chip communication architecture is a major determinant of overall performance in complex System-on-Chip (SoC) designs. Since the communication requirements of SoC components...
Krishna Sekar, Kanishka Lahiri, Anand Raghunathan,...
TVLSI
2008
139views more  TVLSI 2008»
13 years 4 months ago
Ternary CAM Power and Delay Model: Extensions and Uses
Applications in computer networks often require high throughput access to large data structures for lookup and classification. While advanced algorithms exist to speed these search...
Banit Agrawal, Timothy Sherwood
TVLSI
2008
119views more  TVLSI 2008»
13 years 4 months ago
Automatic Design of Reconfigurable Domain-Specific Flexible Cores
Reconfigurable hardware is ideal for use in Systems-on-a-Chip, as it provides both hardware-level performance and post-fabrication flexibility. However, any one architecture is ra...
Katherine Compton, Scott Hauck
TVLSI
2008
110views more  TVLSI 2008»
13 years 4 months ago
Thermal Switching Error Versus Delay Tradeoffs in Clocked QCA Circuits
Abstract--The quantum-dot cellular automata (QCA) model offers a novel nano-domain computing architecture by mapping the intended logic onto the lowest energy configuration of a co...
Sanjukta Bhanja, Sudeep Sarkar
TVLSI
2008
89views more  TVLSI 2008»
13 years 4 months ago
Test Set Development for Cache Memory in Modern Microprocessors
Up to 53% of the time spent on testing current Intel microprocessors is needed to test on-chip caches, due to the high complexity of memory tests and to the large amount of transis...
Zaid Al-Ars, Said Hamdioui, Georgi Gaydadjiev, Sta...