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TVLSI
2010
8 years 26 days ago
Discrete Buffer and Wire Sizing for Link-Based Non-Tree Clock Networks
Clock network is a vulnerable victim of variations as well as a main power consumer in many integrated circuits. Recently, link-based non-tree clock network attracts people's...
Rupak Samanta, Jiang Hu, Peng Li
TVLSI
2010
8 years 26 days ago
Enhancing the Area Efficiency of FPGAs With Hard Circuits Using Shadow Clusters
There is a dramatic logic density gap between FPGAs and ASICs, and this gap is the main reason FPGAs are not cost-effective in high volume applications. Modern FPGAs narrow this ga...
Peter A. Jamieson, Jonathan Rose
TVLSI
2010
8 years 26 days ago
Accurate Predictive Interconnect Modeling for System-Level Design
Luca P. Carloni, Andrew B. Kahng, Sudhakar Muddu, ...
TVLSI
2010
8 years 26 days ago
Asynchronous Data-Driven Circuit Synthesis
A method is described for synthesizing asynchronous circuits based on the Handshake Circuit paradigm but employing a data-driven, rather than a control-driven, style. This approach...
Sam Taylor, Doug A. Edwards, Luis A. Plana, Luis A...
TVLSI
2010
8 years 26 days ago
Bandwidth Adaptive Hardware Architecture of K-Means Clustering for Video Analysis
K-Means is a clustering algorithm that is widely applied in many fields, including pattern classification and multimedia analysis. Due to real-time requirements and computational-c...
Tse-Wei Chen, Shao-Yi Chien
TVLSI
2010
8 years 26 days ago
A Low-Cost VLSI Implementation for Efficient Removal of Impulse Noise
Abstract--Image and video signals might be corrupted by impulse noise in the process of signal acquisition and transmission. In this paper, an efficient VLSI implementation for rem...
Pei-Yin Chen, Chih-Yuan Lien, Hsu-Ming Chuang
TVLSI
2010
8 years 26 days ago
Low-Power Multimedia System Design by Aggressive Voltage Scaling
Mobile multimedia systems are growing in complexity, scalability and thus correspondingly in their implementation challenges. By design, these systems have built-in error resilienc...
Fadi J. Kurdahi, Ahmed M. Eltawil, Kang Yi, Stanle...
TVLSI
2010
8 years 26 days ago
LOPASS: A Low-Power Architectural Synthesis System for FPGAs With Interconnect Estimation and Optimization
In this paper, we present a low-power architectural synthesis system (LOPASS) for field-programmable gate-array (FPGA) designs with interconnect power estimation and optimization. ...
Deming Chen, Jason Cong, Yiping Fan, Lu Wan
TVLSI
2010
8 years 26 days ago
Fast Analysis of a Large-Scale Inductive Interconnect by Block-Structure-Preserved Macromodeling
To efficiently analyze the large-scale interconnect dominant circuits with inductive couplings (mutual inductances), this paper introduces a new state matrix, called VNA, to stamp ...
Hao Yu, Chunta Chu, Yiyu Shi, David Smart, Lei He,...
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