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TVLSI
2010
8 years 2 months ago
A Novel Variation-Tolerant Keeper Architecture for High-Performance Low-Power Wide Fan-In Dynamic or Gates
Dynamic gates have been excellent choice in the design of high-performance modules in modern microprocessors. The only limitation of dynamic gates is their relatively low noise mar...
Hamed F. Dadgour, Kaustav Banerjee
TVLSI
2010
8 years 2 months ago
Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...
Meikang Qiu, Laurence Tianruo Yang, Zili Shao, Edw...
TVLSI
2010
8 years 2 months ago
Design and Implementation of a Sort-Free K-Best Sphere Decoder
:- This paper describes the design and VLSI architecture for a 4x4 breadth first K-Best MIMO decoder using a 64 QAM scheme. A novel sort free approach to path extension, as well as...
Sudip Mondal, Ahmed M. Eltawil, Chung-An Shen, Kha...
TVLSI
2010
8 years 2 months ago
On the Power Management of Simultaneous Multithreading Processors
SMT processors are widely used in high performance computing tasks. However, with the improved performance of the SMT architecture, the utilization of their functional units is sig...
Ahmed Youssef, Mohamed Zahran, Mohab Anis, Mohamed...
TVLSI
2010
8 years 2 months ago
Improving FPGA Performance for Carry-Save Arithmetic
The selective use of carry-save arithmetic, where appropriate, can accelerate a variety of arithmetic-dominated circuits. Carry-save arithmetic occurs naturally in a variety of DSP...
Hadi Parandeh-Afshar, Ajay K. Verma, Philip Brisk,...
TVLSI
2010
8 years 2 months ago
Area and Power Optimization of High-Order Gain Calibration in Digitally-Enhanced Pipelined ADCs
Digital calibration techniques are widely utilized to linearize pipelined analog-to-digital converters (ADCs). However, their power dissipation can be prohibitively high, particula...
Mohammad Taherzadeh-Sani, Anas A. Hamoui
TVLSI
2010
8 years 2 months ago
SRAM Read/Write Margin Enhancements Using FinFETs
Process-induced variations and sub-threshold leakage in bulk-Si technology limit the scaling of SRAM into sub-32 nm nodes. New device architectures are being considered to improve ...
Andrew Carlson, Zheng Guo, Sriram Balasubramanian,...
TVLSI
2010
8 years 2 months ago
Pattern Sensitive Placement Perturbation for Manufacturability
The gap between VLSI technology and fabrication technology leads to strong refractive effects in lithography. Consequently, it is a huge challenge to reliably print layout features...
Shiyan Hu, Patrik Shah, Jiang Hu
TVLSI
2010
8 years 2 months ago
Test Data Compression Using Efficient Bitmask and Dictionary Selection Methods
Abstract--Higher circuit densities in system-on-chip (SOC) designs have led to drastic increase in test data volume. Larger test data size demands not only higher memory requiremen...
Kanad Basu, Prabhat Mishra
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