Sciweavers

DAC
2005
ACM
14 years 5 months ago
Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction
To reduce power, Vdd programmability has been proposed recently to select Vdd-level for interconnects and to powergate unused interconnects. However, Vdd-level converters used in ...
Yan Lin, Lei He