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EURODAC
1994
IEEE
149views VHDL» more  EURODAC 1994»
8 years 7 months ago
A flexible access control mechanism for CAD frameworks
A. J. van der Hoeven, K. Olav ten Bosch, Rene van ...
EURODAC
1994
IEEE
110views VHDL» more  EURODAC 1994»
8 years 7 months ago
An experimental analysis of the effectiveness of the circular self-test path technique
Paolo Prinetto, Fulvio Corno, Matteo Sonza Reorda
EURODAC
1994
IEEE
148views VHDL» more  EURODAC 1994»
8 years 7 months ago
System-Level Modeling and Verification: a Comprehensive Design Methodology
Paolo Camurati, Fulvio Corno, Paolo Prinetto, Cath...
EURODAC
1995
IEEE
148views VHDL» more  EURODAC 1995»
8 years 8 months ago
Software system for semiconductor devices, monolith and hybrid ICs thermal analysis
A three level software system for thermal analysis of semiconductor devices, one-chip monolith IC's, multi-chip modules (MCM) and hybrid IC's is presented. For each desig...
Konstantin O. Petrosjanc, I. A. Kharitonov, N. I. ...
EURODAC
1995
IEEE
133views VHDL» more  EURODAC 1995»
8 years 8 months ago
Tree restructuring approach to mapping problem in cellular-architecture FPGAs
A new technique for mapping combinational circuits to Fine-Grain Cellular-Architecture FPGAs is presented. The proposed tree restructuring algorithm preserves local connectivity a...
Naveen Ramineni, Malgorzata Chrzanowska-Jeske, Nav...
EURODAC
1995
IEEE
162views VHDL» more  EURODAC 1995»
8 years 8 months ago
ODE: output direct state machine encoding
A somewhat novel approach is presented for determining FSM state codes. Instead of producing an assignment designed to minimise the overall logic of the machine, all Moore outputs...
J. Forrest
EURODAC
1995
IEEE
159views VHDL» more  EURODAC 1995»
8 years 8 months ago
Performance-oriented placement and routing for field-programmable gate arrays
This paper presents a performance-oriented placement and routing tool for field-programmable gate arrays. Using recursive geometric partitioning for simultaneous placement and glo...
Michael J. Alexander, James P. Cohoon, Joseph L. G...
EURODAC
1995
IEEE
195views VHDL» more  EURODAC 1995»
8 years 8 months ago
A hardware/software partitioning algorithm for pipelined instruction set processor
This paper proposes a new method to design an optimal instruction set for pipelined ASIP development using a formal HW/SW codesign methodology. The codesign task addressed in this...
Binh Ngoc Nguyen, Masaharu Imai, Nobuyuki Hikichi
EURODAC
1995
IEEE
182views VHDL» more  EURODAC 1995»
8 years 8 months ago
Delay modelling improvement for low voltage applications
Based on an explicit formulation of delays, an improved model for low voltage operation of CMOS inverter has been derived. Extrinsic and intrinsic effects, such as transistor curr...
Jean Michel Daga, Michel Robert, Daniel Auvergne
EURODAC
1995
IEEE
117views VHDL» more  EURODAC 1995»
8 years 8 months ago
Performance-complexity analysis in hardware-software codesign for real-time systems
The paper presents an approach for performance and complexity analysis of hardware/software implementations for real-time systems on every stage of the partitioning. There are two...
Victor V. Toporkov
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