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EURODAC
1995
IEEE
156views VHDL» more  EURODAC 1995»
8 years 9 months ago
KANDIS - a tool for construction of mixed analog/digital systems
The synthesis of electronic circuits on system level o ers the possibility to nd better locations of the A/D interfaces and to determine parameters like clock rates and bit widths...
Peter Oehler, Christoph Grimm, Klaus Waldschmidt
EURODAC
1995
IEEE
155views VHDL» more  EURODAC 1995»
8 years 9 months ago
Design and use of a system-level specification and verification methodology
M. M. Kamal Hashmi, Alistair C. Bruce
EURODAC
1995
IEEE
151views VHDL» more  EURODAC 1995»
8 years 9 months ago
Model of conceptual design of complex electronic systems
Due to the ever increasing complexity of electronic system (ES) design, the conceptual design phase and its realization in later phases of the design stream have become increasing...
Alexander N. Soloviev, Alexander L. Stempkovsky
EURODAC
1995
IEEE
135views VHDL» more  EURODAC 1995»
8 years 9 months ago
A high performance VHDL simulator for large systems design
The requirements of large system design place great demands upon the performance and diagnostic capabilities of simulation. This paper explains how these requirements have been sa...
Steve Hodgson, Zak Shaar, Andy Smith
EURODAC
1995
IEEE
101views VHDL» more  EURODAC 1995»
8 years 9 months ago
Exploiting power-up delay for sequential optimization
Recent work has identified the notion of safe replacement for sequential synchronousdesigns that may not have reset hardware or even explicitly known initial states. Safe replace...
Vigyan Singhal, Carl Pixley, Adnan Aziz, Robert K....
EURODAC
1995
IEEE
130views VHDL» more  EURODAC 1995»
8 years 9 months ago
Semi-dynamic scheduling of synchronization-mechanisms
This paper presents a novel approach to scheduling of hardware supported synchronization operations. The optimization goal is to minimize the interation time of processes and thus...
Wolfgang Ecker
EURODAC
1995
IEEE
180views VHDL» more  EURODAC 1995»
8 years 9 months ago
Integration of VHDL into a system design environment
Verification of image processing systems is mainly done on the basis of image sequence simulations. To achieve high simulation efficiency, our compiled code simulator MSIPC offers...
Ludwig Schwoerer, Matthias Lück, Hartmut Schr...
EURODAC
1995
IEEE
131views VHDL» more  EURODAC 1995»
8 years 9 months ago
System level design, a VHDL based approach
A hierarchical system design flow was developed to facilitate concurrent development and Time-to-Market reductions. The system design flow provides for codesign of (embedded) driv...
Joris van den Hurk, Edwin Dilling
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