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MICRO
1999
IEEE
108views Hardware» more  MICRO 1999»
11 years 9 months ago
Exploiting ILP in Page-based Intelligent Memory
This study compares the speed, area, and power of di erent implementations of Active Pages OCS98], an intelligent memory system which helps bridge the growing gap between processo...
Mark Oskin, Justin Hensley, Diana Keen, Frederic T...
HPCC
2009
Springer
11 years 10 months ago
On Instruction-Level Method for Reducing Cache Penalties in Embedded VLIW Processors
Usual cache optimisation techniques for high performance computing are dif´Čücult to apply in embedded VLIW applications. First, embedded applications are not always well structur...
Samir Ammenouche, Sid Ahmed Ali Touati, William Ja...
ISSS
2002
IEEE
174views Hardware» more  ISSS 2002»
11 years 10 months ago
A Run-Time Word-Level Reconfigurable Coarse-Grain Functional Unit for a VLIW Processor
Nowadays, new DSP applications are offering combined and flexible multimedia and telecom services. VLIW processor architectures, which include dedicated but inflexible functional ...
Carles Rodoreda Sala, Natalino G. Busá
DATE
2003
IEEE
99views Hardware» more  DATE 2003»
11 years 10 months ago
Instruction Set Emulation for Rapid Prototyping of SoCs
In this paper the application of Instruction Set Emulation for rapid prototyping of SoCs will be presented. The emulation works in a way that both the software and the hardware be...
Jürgen Schnerr, Gunter Haug, Wolfgang Rosenst...
DATE
2003
IEEE
109views Hardware» more  DATE 2003»
11 years 10 months ago
A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors
This paper presents a new algorithm for on-the-fly data compression in high performance VLIW processors. The algorithm aggressively targets energy minimization of some of the domi...
Alberto Macii, Enrico Macii, Fabrizio Crudo, Rober...
DATE
2005
IEEE
187views Hardware» more  DATE 2005»
11 years 11 months ago
Cycle Accurate Binary Translation for Simulation Acceleration in Rapid Prototyping of SoCs
In this paper, the application of a cycle accurate binary translator for rapid prototyping of SoCs will be presented. This translator generates code to run on a rapid prototyping ...
Jürgen Schnerr, Oliver Bringmann, Wolfgang Ro...
CODES
2007
IEEE
11 years 11 months ago
A low power VLIW processor generation method by means of extracting non-redundant activation conditions
This paper proposes a low power VLIW processor generation method by automatically extracting non-redundant activation conditions of pipeline registers for clock gating. It is impo...
Hirofumi Iwato, Keishi Sakanushi, Yoshinori Takeuc...
VLSID
2007
IEEE
98views VLSI» more  VLSID 2007»
12 years 5 months ago
Power Reduction in VLIW Processor with Compiler Driven Bypass Network
Neeraj Goel, Anshul Kumar, Preeti Ranjan Panda
books