Sciweavers

ARITH
2011
IEEE
12 years 4 months ago
Fast Ripple-Carry Adders in Standard-Cell CMOS VLSI
— This paper presents a number of new high-radix ripple-carry adder designs based on Ling’s addition technique and a recently-published expansion thereof. The proposed adders a...
Neil Burgess
DAC
1995
ACM
13 years 8 months ago
A Survey of Optimization Techniques Targeting Low Power VLSI Circuits
—We survey state-of-the-art optimization methods that target low power dissipation in VLSI circuits. Optimizations at the circuit, logic, architectural and system levels are cons...
Srinivas Devadas, Sharad Malik
DAC
1996
ACM
13 years 8 months ago
Partitioning of VLSI Circuits and Systems
Partitioning plays an increasingly important role in the design process of VLSI circuits and systems. There are partitioning to be solved on all levels of abstraction. The rapidly...
Frank M. Johannes
DFT
2003
IEEE
106views VLSI» more  DFT 2003»
13 years 9 months ago
Techniques for Transient Fault Sensitivity Analysis and Reduction in VLSI Circuits
Transient faults in VLSI circuits could lead to disastrous consequences. With technology scaling, circuits are becoming increasingly vulnerable to transient faults. This papers pr...
Atul Maheshwari, Israel Koren, Wayne Burleson
ISQED
2006
IEEE
153views Hardware» more  ISQED 2006»
13 years 10 months ago
Improving Transient Error Tolerance of Digital VLSI Circuits Using RObustness COmpiler (ROCO)
Due to aggressive technology scaling, VLSI circuits are becoming increasingly susceptible to transient errors caused by single-event-upsets (SEUs). In this paper, we introduce two...
Chong Zhao, Sujit Dey
DSD
2009
IEEE
111views Hardware» more  DSD 2009»
13 years 11 months ago
Robustness Check for Multiple Faults Using Formal Techniques
Feature sizes in VLSI circuits are steadily shrinking. This results in increasing susceptibility to soft errors, e.g. due to environmental radiation. Precautions against soft error...
Stefan Frehse, Görschwin Fey, André S&...
ICCAD
2003
IEEE
114views Hardware» more  ICCAD 2003»
14 years 1 months ago
A Novel Geometric Algorithm for Fast Wire-Optimized Floorplanning
As the size and complexity of VLSI circuits increase, the need for faster floorplanning algorithms also grows. In this work we introduce Traffic, a new method for creating wire- a...
Peter G. Sassone, Sung Kyu Lim