ISPD
2012
ACM
12 years 3 days ago
2012
ACM
Gate sizing in VLSI design is a widely-used method for power or area recovery subject to timing constraints. Several previous works have proposed gate sizing heuristics for power ...
ISJGP
2010
13 years 1 months ago
2010
A variety of modern technologies such as networks, Internet, and electronic services demand private and secure communications for a great number of everyday transactions. Security ...
CCCG
2009
13 years 5 months ago
2009
Design Rule Checking (DRC) in VLSI design involves checking if a given VLSI layout satisfies a given set of rules, and reporting the violations if any. We propose data structures ...
DAC
1998
ACM
13 years 8 months ago
1998
ACM
This paper considers the rate optimal VLSI design of a recursive data flow graph (DFG). Previous research on rate optimal scheduling is not directly applicable to VLSI design. We ...
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