Sciweavers

FCCM
2004
IEEE
112views VLSI» more  FCCM 2004»
13 years 8 months ago
ShareStreams: A Scalable Architecture and Hardware Support for High-Speed QoS Packet Schedulers
Raj Krishnamurthy, Sudhakar Yalamanchili, Karsten ...
FCCM
2004
IEEE
97views VLSI» more  FCCM 2004»
13 years 8 months ago
Unidirectional Switch-Boxes for Synthesizable Reconfigurable Arrays
Sami Khawam, Tughrul Arslan, Fred Westall
FCCM
2004
IEEE
121views VLSI» more  FCCM 2004»
13 years 8 months ago
A 21.54 Gbits/s Fully Pipelined AES Processor on FPGA
Alireza Hodjat, Ingrid Verbauwhede
FCCM
2004
IEEE
91views VLSI» more  FCCM 2004»
13 years 8 months ago
An FPGA Interpolation Processor for Soft-Decision Reed-Solomon Decoding
We propose a parallel architecture for implementing the interpolation step in the Koetter-Vardy soft-decision ReedSolomon decoding algorithm. The key feature is the embedding of b...
Warren J. Gross, Frank R. Kschischang, P. Glenn Gu...
FCCM
2004
IEEE
141views VLSI» more  FCCM 2004»
13 years 8 months ago
Deep Packet Filter with Dedicated Logic and Read Only Memories
Searching for multiple string patterns in a stream of data is a computationally expensive task. The speed of the search pattern module determines the overall performance of deep p...
Young H. Cho, William H. Mangione-Smith
FCCM
2004
IEEE
98views VLSI» more  FCCM 2004»
13 years 8 months ago
Automated Least-Significant Bit Datapath Optimization for FPGAs
In this paper we present a method for FPGA datapath precision optimization subject to user-defined area and error constraints. This work builds upon our previous research [1] which...
Mark L. Chang, Scott Hauck
FCCM
2004
IEEE
144views VLSI» more  FCCM 2004»
13 years 8 months ago
Efficient Execution of Process Networks on a Reconfigurable Hardware Virtual Machine
In this paper we present a novel use of an FPGA as a computing element for streaming based application. We investigate the virtualized execution of dynamic reconfigurable tasks. We...
Matthias Dyer, Marco Platzner, Lothar Thiele
FCCM
2004
IEEE
269views VLSI» more  FCCM 2004»
13 years 8 months ago
FPGA Based Network Intrusion Detection using Content Addressable Memories
In this paper, we introduce a novel architecture for a hardware based network intrusion detection system (NIDS). Current software-based NIDS are too compute intensive and can not ...
Long Bu, John A. Chandy
FCCM
2004
IEEE
129views VLSI» more  FCCM 2004»
13 years 8 months ago
Design Patterns for Reconfigurable Computing
It is valuable to identify and catalog design patterns for reconfigurable computing. These design patterns are canonical solutions to common and recurring design challenges which ...
André DeHon, Joshua Adams, Michael DeLorimi...
FCCM
2004
IEEE
133views VLSI» more  FCCM 2004»
13 years 8 months ago
A Methodology for Synthesis of Efficient Intrusion Detection Systems on FPGAs
Intrusion detection for network security is a computation intensive application demanding high system performance. System level design, a relatively unexplored field in this area,...
Zachary K. Baker, Viktor K. Prasanna