Sciweavers

GLVLSI
2007
IEEE
187views VLSI» more  GLVLSI 2007»
13 years 10 months ago
DAG based library-free technology mapping
This paper proposes a library-free technology mapping algorithm to reduce delay in combinational circuits. The algorithm reduces the overall number of series transistors through t...
Felipe S. Marques, Leomar S. da Rosa Jr., Renato P...
GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Analyzing and modeling process balance for sub-threshold circuit design
Joseph F. Ryan, Jiajing Wang, Benton H. Calhoun
GLVLSI
2007
IEEE
154views VLSI» more  GLVLSI 2007»
13 years 10 months ago
A design kit for a fully working shared memory multiprocessor on FPGA
This paper presents a framework to design a shared memory multiprocessor on a programmable platform. We propose a complete flow, composed by a programming model and a template ar...
Antonino Tumeo, Matteo Monchiero, Gianluca Palermo...
GLVLSI
2007
IEEE
167views VLSI» more  GLVLSI 2007»
13 years 10 months ago
A new approach to logic synthesis of multi-output boolean functions on pal-based CPLDS
A PAL-based logic block is the core of great majority of contemporary CPLD devices. The purpose of the paper is to present a new approach to multi-level synthesis for PAL-based CP...
Dariusz Kania
GLVLSI
2007
IEEE
135views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Exact sat-based toffoli network synthesis
Compact realizations of reversible logic functions are of interest in the design of quantum computers. Such reversible functions are realized as a cascade of Toffoli gates. In th...
Daniel Große, Xiaobo Chen, Gerhard W. Dueck,...
GLVLSI
2007
IEEE
141views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Transition-activity aware design of reduction-stages for parallel multipliers
We propose an interconnect reorganization algorithm for reduction stages in parallel multipliers. It aims at minimizing power consumption for given static probabilities at the pri...
Saeeid Tahmasbi Oskuii, Per Gunnar Kjeldsberg, Osc...
GLVLSI
2007
IEEE
177views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Improvements for constraint solving in the systemc verification library
Daniel Große, Rüdiger Ebendt, Rolf Drec...
GLVLSI
2007
IEEE
192views VLSI» more  GLVLSI 2007»
13 years 10 months ago
Area efficient loop filter design for charge pump phase locked loop
In this paper, two new dual-path based area efficient loop filter circuits are proposed for Charge Pump Phase Locked Loop (CPPLL). The proposed circuits were designed in 0.25µ CS...
R. G. Raghavendra, Bharadwaj Amrutur
VTS
2008
IEEE
104views Hardware» more  VTS 2008»
13 years 10 months ago
Signature Rollback - A Technique for Testing Robust Circuits
Dealing with static and dynamic parameter variations has become a major challenge for design and test. To avoid unnecessary yield loss and to ensure reliable system operation a ro...
Uranmandakh Amgalan, Christian Hachmann, Sybille H...