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VLSID
2000
IEEE
135views VLSI» more  VLSID 2000»
11 years 11 months ago
Performance and Functional Verification of Microprocessors
We address the problem of verifying the correctness of pre-silicon models of a microprocessor. We touch on the latest advances in this area by considering two different aspects of...
Pradip Bose, Jacob A. Abraham
VLSID
2000
IEEE
85views VLSI» more  VLSID 2000»
12 years 10 days ago
A Fast Graph-Based Alternative Wiring Scheme for Boolean Networks
Yu-Liang Wu, Wangning Long, Hongbing Fan
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
12 years 10 days ago
Energy Aware Software
Amit Sinha, Anantha Chandrakasan
VLSID
2000
IEEE
76views VLSI» more  VLSID 2000»
12 years 10 days ago
Optimal Hardware/Software Partitioning for Concurrent Specification Using Dynamic Programming
Aviral Shrivastava, Mohit Kumar, Sanjiv Kapoor, Sh...
VLSID
2000
IEEE
102views VLSI» more  VLSID 2000»
12 years 10 days ago
Inductance Characterization of Small Interconnects Using Test-Signal Method
The test signal method can be used to measure and model inductance parameters (self and mutual) of a very small interconnect especially in highdensity IC’s by using a test signa...
Jeegar Tilak Shah, Madhav P. Desai, Sugata Sanyal
VLSID
2000
IEEE
121views VLSI» more  VLSID 2000»
12 years 10 days ago
Design of Synchronous Action Systems
The action systems framework has recently been applied to the area of synchronous VLSI design. In this paper, we present a set of concepts necessary in the formal design of synchr...
Juha Plosila, Tiberiu Seceleanu
VLSID
2000
IEEE
79views VLSI» more  VLSID 2000»
12 years 10 days ago
Inductive Noise Reduction at the Architectural Level
A methodology for reducing ground bounce in typical microprocessors and image processing architectures has been described. As we approach Gigascale Integration, chip power consump...
Mondira Deb Pant, Pankaj Pant, D. Scott Wills, Viv...
VLSID
2000
IEEE
98views VLSI» more  VLSID 2000»
12 years 10 days ago
Low Power Realization of Residue Number System Based FIR Filters
M. N. Mahesh, Mahesh Mehendale
VLSID
2000
IEEE
94views VLSI» more  VLSID 2000»
12 years 10 days ago
A Genetic Algorithm for the Synthesis of Structured Data Paths
The technique presented here achieves simultaneous optimization of schedule time and data path component cost within a structured data path architecture, using a genetic algorithm...
Chittaranjan A. Mandal, R. M. Zimmer
VLSID
2000
IEEE
90views VLSI» more  VLSID 2000»
12 years 10 days ago
Performance Analysis of Systems with Multi-Channel Communication Architectures
This paper presents a novel system performance analysis technique to support the design of custom communication architectures for System-on-Chip ICs. Our technique fills a gap in...
Kanishka Lahiri, Sujit Dey, Anand Raghunathan
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