VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
à This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic t...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
VLSID
2002
IEEE
13 years 9 months ago
2002
IEEE
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire recon...
VLSID
2002
IEEE
14 years 4 months ago
2002
IEEE
CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...