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VLSID
2002
IEEE
114views VLSI» more  VLSID 2002»
11 years 3 months ago
Minimizing Energy Consumption for High-Performance Processing
Power consumption is becoming an increasingly important constraint in the design of microprocessors. This paper examines the use of multiple constrained processors running at lowe...
Eric F. Weglarz, Kewal K. Saluja, Mikko H. Lipasti
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
11 years 3 months ago
Power Supply Noise Aware Floorplanning and Decoupling Capacitance Placement
Power supply noise is a strong function of the switching activities of the circuit modules. Peak power supply noise can be significantly reduced by judiciously arranging the modu...
Shiyou Zhao, Kaushik Roy, Cheng-Kok Koh
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
11 years 3 months ago
An Adaptive Interconnect-Length Driven Placer
Chi-Ming Tsai, Kun-Tien Kuo, Chyi-Hui Hong, Rung-B...
VLSID
2002
IEEE
81views VLSI» more  VLSID 2002»
11 years 3 months ago
A New Synthesis of Symmetric Functions
A new approach to synthesizing totally symmetric Boolean functions is presented. First, a novel cellular array is introduced for synthesizing unate symmetric functions. Using this...
Hafizur Rahaman, Debesh K. Das, Bhargab B. Bhattac...
VLSID
2002
IEEE
192views VLSI» more  VLSID 2002»
11 years 3 months ago
Static and Dynamic Variable Voltage Scheduling Algorithms for Real-Time Heterogeneous Distributed Embedded Systems
à This paper addresses the problem of static and dynamic variable voltage scheduling of multi-rate periodic task graphs (i.e., tasks with precedence relationships) and aperiodic t...
Jiong Luo, Niraj K. Jha
VLSID
2002
IEEE
96views VLSI» more  VLSID 2002»
11 years 3 months ago
Strategies for Improving Data Locality in Embedded Applications
This paper introduces a dynamic layout optimization strategy to minimize the number of cycles spent in memory accesses in a cache-based memory environment. In this approach, a giv...
N. E. Crosbie, Mahmut T. Kandemir, Ibrahim Kolcu, ...
VLSID
2002
IEEE
100views VLSI» more  VLSID 2002»
11 years 3 months ago
Layout-Driven Timing Optimization by Generalized De Morgan Transform
We propose a timing-oriented logic optimization technique called Generalized De Morgan (GDM) transform, that integrates gate resizing, net buffering and De Morgan transformation. ...
Supratik Chakraborty, Rajeev Murgai
VLSID
2002
IEEE
115views VLSI» more  VLSID 2002»
11 years 10 months ago
Logic Synthesis for AND-XOR-OR Type Sense-Amplifying PLA
In this paper, a new logic synthesis method for an AND-XOR-OR type sense-amplifying PLA is proposed. An AND-XOR-OR type sense-amplifying PLA can achieve lowpower dissipation and h...
Hiroaki Yoshida, Hiroaki Yamaoka, Makoto Ikeda, Ku...
VLSID
2002
IEEE
87views VLSI» more  VLSID 2002»
11 years 10 months ago
Simultaneous Circuit Transformation and Routing
In this paper, we propose a new methodology to integrate circuit transformation into routing. More specifically, this paper shows an approach for performing routing and wire recon...
Hiroaki Yoshida, Motohiro Sera, Masao Kubo, Masahi...
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
11 years 10 months ago
IEEE 1394a_2000 Physical Layer ASIC
CN4011A is IEEE 1394a_2000 standard Compliant Physical Layer ASIC. It is a 0.18um mixed-signal ASIC incorporating three analog ports, PLL, reference generator for analog along wit...
Ranjit Yashwante, Bhalchandra Jahagirdar
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