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VLSID
2002
IEEE
75views VLSI» more  VLSID 2002»
14 years 3 months ago
Explicit Expression and Simultaneous Optimization of Placement and Routing for Analog IC Layouts
Our target is automation of analog circuit's layout, which is a bottleneck in mixed-signal's design. We formulate the layout explicitly considering manufacturing process...
Yukiko Kubo, Shigetoshi Nakatake, Yoji Kajitani, M...
VLSID
2002
IEEE
98views VLSI» more  VLSID 2002»
14 years 3 months ago
On Test Scheduling for Core-Based SOCs
We present a mathematical model for the problem of scheduling tests for core-based system-on-chip (SOC) VLSI designs. Given a set of tests for each core in the SOC and a set of te...
Sandeep Koranne
VLSID
2002
IEEE
91views VLSI» more  VLSID 2002»
14 years 3 months ago
Rational ABCD Modeling of High-Speed Interconnects
This paper introduces a new numerical approximation technique, called the Differential Quadrature Method (DQM), in order to derive the rational ABCD matrix representing the high-s...
Qinwei Xu, Pinaki Mazumder
VLSID
2002
IEEE
97views VLSI» more  VLSID 2002»
14 years 3 months ago
Multiple Faults: Modeling, Simulation and Test
We give an algorithm to model any given multiple stuck-at fault as a single stuck-at fault. The procedure requires insertion of at most ? ? ? modeling gates, when the multiplicity...
Yong Chang Kim, Vishwani D. Agrawal, Kewal K. Salu...
VLSID
2002
IEEE
128views VLSI» more  VLSID 2002»
14 years 3 months ago
System-Level Point-to-Point Communication Synthesis using Floorplanning Information
: In this paper, we present a point-to-point (P2P) communication synthesis methodology for SystemOn-Chip (SOC) design. We consider real-time systems where IP selection, mapping and...
Jingcao Hu, Yangdong Deng, Radu Marculescu
VLSID
2002
IEEE
74views VLSI» more  VLSID 2002»
14 years 3 months ago
Interconnect Energy Dissipation in High-Speed ULSI Circuits
- This work presents accurate closed-form expressions for the interconnect energy dissipation in high-speed ULSI circuits. Unlike previous works, the energy is calculated using an ...
Payam Heydari, Massoud Pedram
VLSID
2002
IEEE
106views VLSI» more  VLSID 2002»
14 years 3 months ago
SWASAD: An ASIC Design for High Speed DNA Sequence Matching
This paper presents the Smith and Waterman Algorithm-Specific ASIC Design (SWASAD) project. This is a hardware solution that implements the S&W algorithm.. The SWASAD is an imp...
Tony Han, Sri Parameswaran
VLSID
2002
IEEE
95views VLSI» more  VLSID 2002»
14 years 3 months ago
Design of an On-Chip Test Pattern Generator without Prohibited Pattern Set (PPS)
| This paper reports the design of a Test Pattern Generator (TPG) for VLSI circuits. The onchip TPG is so designed that it generates test patterns while avoiding generation of a gi...
Niloy Ganguly, Biplab K. Sikdar, Parimal Pal Chaud...
VLSID
2002
IEEE
149views VLSI» more  VLSID 2002»
14 years 3 months ago
Functional Partitioning for Low Power Distributed Systems of Systems-on-a-Chip
In this paper, we present a functional partitioning method for low power real-time distributed embedded systems whose constituent nodes are systems-on-a-chip (SOCs). The systemlev...
Yunsi Fei, Niraj K. Jha
VLSID
2002
IEEE
122views VLSI» more  VLSID 2002»
14 years 3 months ago
Evaluating Run-Time Techniques for Leakage Power Reduction
While some leakage power reduction techniques require modification of process technology achieving savings at the fabrication stage, others are based on circuit-level optimization...
David Duarte, Yuh-Fang Tsai, Narayanan Vijaykrishn...