VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Reduction of worst-case delay and delay uncertainty due to capacitive coupling is a still unsolved problem in physical design. We describe a routing only layout solution - swizzli...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Dynamic noise analysis is greatly needed in place of traditional static noise analysis due to the ever increasingly stringent design requirement for VLSI chips based on very deep ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
System-on-Chip (SoC) design methodologies rely heavily on reuse of intellectual property (IP) blocks. IP reuse is a labour intensive and time consuming process as IP blocks often ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Power consumption has become a major design limiter. With the continued reduction of threshold voltages, optimizing leakage energy consumption is becoming increasingly important. ...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
In this paper, we describe NoCGEN, a Network On Chip (NoC) generator, which is used to create a simulatable and synthesizable NoC description. NoCGEN uses a set of modularised rou...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
The design of any application on a configurable System-on-a-Chip (SoC) like Atmel's FPSLIC is subject to a lot of constraints stemming from requirements of the application an...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
Abstract--In this paper, we present a new approach to calculate the steady state resistance values for CMOS library gates. These resistances are defined as simple equivalent models...
VLSID
2004
IEEE
14 years 5 months ago
2004
IEEE
