Sciweavers

VLSID
2005
IEEE
224views VLSI» more  VLSID 2005»
14 years 4 months ago
Accurate Stacking Effect Macro-Modeling of Leakage Power in Sub-100nm Circuits
An accurate and efficient stacking effect macro-model for leakage power in sub-100nm circuits is presented in this paper. Leakage power, including subthreshold leakage power and ga...
Shengqi Yang, Wayne Wolf, Narayanan Vijaykrishnan,...
VLSID
2005
IEEE
150views VLSI» more  VLSID 2005»
14 years 4 months ago
Multivariate Normal Distribution Based Statistical Timing Analysis Using Global Projection and Local Expansion
This paper employs general multivariate normal distribution to develop a new efficient statistical timing analysis methodology. The paper presents the theoretical framework of the...
Baohua Wang, Pinaki Mazumder
VLSID
2005
IEEE
158views VLSI» more  VLSID 2005»
14 years 4 months ago
Algorithmic Implementation of Low-Power High Performance FIR Filtering IP Cores
This paper presents two schemes for the implementation of high performance and low power FIR filtering Intellectual Property (IP) cores. Low power is achieved through the utilizat...
C. H. Wang, Ahmet T. Erdogan, Tughrul Arslan
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 4 months ago
A Fast Buffered Routing Tree Construction Algorithm under Accurate Delay Model
Buffer insertion method plays a great role in modern VLSI design. Many buffer insertion algorithms have been proposed in recent years. However, most of them used simplified delay ...
Yibo Wang, Yici Cai, Xianlong Hong
VLSID
2005
IEEE
100views VLSI» more  VLSID 2005»
14 years 4 months ago
Implementing LDPC Decoding on Network-on-Chip
Low-Density Parity Check codes are a form of Error Correcting Codes used in various wireless communication applications and in disk drives. While LDPC codes are desirable due to t...
Theo Theocharides, Greg M. Link, Narayanan Vijaykr...
VLSID
2005
IEEE
132views VLSI» more  VLSID 2005»
14 years 4 months ago
Influence of Leakage Reduction Techniques on Delay/Leakage Uncertainty
One of the main challenges for design in the presence of process variations is to cope with the uncertainties in delay and leakage power. In this paper, the influence of leakage r...
Yuh-Fang Tsai, Narayanan Vijaykrishnan, Yuan Xie, ...
VLSID
2005
IEEE
98views VLSI» more  VLSID 2005»
14 years 4 months ago
False Path and Clock Scheduling Based Yield-Aware Gate Sizing
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
Jeng-Liang Tsai, Dong Hyun Baik, Charlie Chung-Pin...
VLSID
2005
IEEE
121views VLSI» more  VLSID 2005»
14 years 4 months ago
Impact of Channel Engineering on Unity Gain Frequency and Noise-Figure in 90nm NMOS Transistor for RF Applications
In this paper, we have studied and compared the RF performance metrics, unity gain frequency (ft) and Noise Figure (NF), of the devices with channel engineering consisting of halo...
R. Srinivasan, Navakanta Bhat
VLSID
2005
IEEE
126views VLSI» more  VLSID 2005»
14 years 4 months ago
Exact Analytical Equations for Predicting Nonlinear Phase Errors and Jitter in Ring Oscillators
In this paper, we present a simple analytical equation for capturing phase errors in 3-stage ring oscillators. The model, based on a simple but useful idealization of the ring osc...
Jaijeet S. Roychowdhury
VLSID
2005
IEEE
118views VLSI» more  VLSID 2005»
14 years 4 months ago
Battery Model for Embedded Systems
This paper explores the recovery and rate capacity effect for batteries used in embedded systems. It describes the prominent battery models with their advantages and drawbacks. It...
Venkat Rao, Gaurav Singhal, Anshul Kumar, Nicolas ...