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VLSISP
2008
61views more  VLSISP 2008»
8 years 7 months ago
A Dynamic Voltage Scaling Algorithm for Dynamic Workloads
Albert Mo Kim Cheng, Yan Wang
VLSISP
2008
103views more  VLSISP 2008»
8 years 7 months ago
Power Signature Watermarking of IP Cores for FPGAs
In this paper, we introduce a new method for watermarking of IP cores for FPGA architectures where the signature (watermark) is detected at the power supply pins of the FPGA. This ...
Daniel Ziener, Jürgen Teich
VLSISP
2008
147views more  VLSISP 2008»
8 years 7 months ago
Data Reuse Exploration for Low Power Motion Estimation Architecture Design in H.264 Encoder
Data access usually leads to more than 50% of the power cost in a modern signal processing system. To realize a low-power design, how to reduce the memory access power is a critica...
Yu-Han Chen, Tung-Chien Chen, Chuan-Yung Tsai, Sun...
VLSISP
2008
191views more  VLSISP 2008»
8 years 8 months ago
Accurate and Scalable Simulation of Network of Heterogeneous Sensor Devices
Simulation is an important tool to study and analyze sensor networks. Prior work in sensor network simulation focuses on homogeneous devices. In this paper, we present a system tha...
Ye Wen, Selim Gurun, Navraj Chohan, Richard Wolski...
VLSISP
2008
104views more  VLSISP 2008»
8 years 9 months ago
Guidance of Loop Ordering for Reduced Memory Usage in Signal Processing Applications
Data dominated signal processing applications are typically described using large and multi-dimensional arrays and loop nests. The order of production and consumption of array ele...
Per Gunnar Kjeldsberg, Francky Catthoor, Sven Verd...
VLSISP
2008
203views more  VLSISP 2008»
8 years 9 months ago
FPGA-based System for Real-Time Video Texture Analysis
This paper describes a novel system for real-time video texture analysis. The system utilizes hardware to extract 2nd -order statistical features from video frames. These features ...
Dimitrios E. Maroulis, Dimitrios K. Iakovidis, Dim...
VLSISP
2008
129views more  VLSISP 2008»
8 years 9 months ago
Architecture and Evaluation of an Asynchronous Array of Simple Processors
Abstract-- This paper presents the architecture of an Asynchronous Array of simple Processors (AsAP), and evaluates its key architectural features as well as its performance and en...
Zhiyi Yu, Michael J. Meeuwsen, Ryan W. Apperson, O...
VLSISP
2008
130views more  VLSISP 2008»
8 years 9 months ago
Analysis and Hardware Architecture Design of Global Motion Estimation
Yi-Hau Chen, Shao-Yi Chien, Ching-Yeh Chen, Yu-Wen...
VLSISP
2008
173views more  VLSISP 2008»
8 years 9 months ago
Fast Bit Gather, Bit Scatter and Bit Permutation Instructions for Commodity Microprocessors
Advanced bit manipulation operations are not efficiently supported by commodity word-oriented microprocessors. Programming tricks are typically devised to shorten the long sequence...
Yedidya Hilewitz, Ruby B. Lee
VLSISP
2008
111views more  VLSISP 2008»
8 years 9 months ago
Design Methodology for Throughput Optimum Architectures of Hash Algorithms of the MD4-class
Abstract. In this paper we propose an architecture design methodology to optimize the throughput of MD4-based hash algorithms. The proposed methodology includes an iteration bound ...
Yong Ki Lee, Herwin Chan, Ingrid Verbauwhede
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