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HPCA
2011
IEEE
8 years 5 months ago
Archipelago: A polymorphic cache design for enabling robust near-threshold operation
Extreme technology integration in the sub-micron regime comes with a rapid rise in heat dissipation and power density for modern processors. Dynamic voltage scaling is a widely us...
Amin Ansari, Shuguang Feng, Shantanu Gupta, Scott ...
TVLSI
2010
8 years 8 months ago
Dynamic and Leakage Energy Minimization With Soft Real-Time Loop Scheduling and Voltage Assignment
With the shrinking of technology feature sizes, the share of leakage in total power consumption of digital systems continues to grow. Traditional dynamic voltage scaling (DVS) fail...
Meikang Qiu, Laurence Tianruo Yang, Zili Shao, Edw...
CORR
2010
Springer
177views Education» more  CORR 2010»
8 years 10 months ago
Dynamic Scheduling of Skippable Periodic Tasks with Energy Efficiency in Weakly Hard Real-Time System
Energy consumption is a critical design issue in real-time systems, especially in battery- operated systems. Maintaining high performance, while extending the battery life between...
Santhi Baskaran, P. Thambidurai
ICCAD
2009
IEEE
87views Hardware» more  ICCAD 2009»
8 years 11 months ago
Mitigation of intra-array SRAM variability using adaptive voltage architecture
SRAM cell design is driven by the need to satisfy static noise margin, write margin and read current margin (RCM) over all cells in the array in an energy-efficient manner. These ...
Ashish Kumar Singh, Ku He, Constantine Caramanis, ...
MICRO
2010
IEEE
132views Hardware» more  MICRO 2010»
8 years 11 months ago
Parichute: Generalized Turbocode-Based Error Correction for Near-Threshold Caches
Energy efficiency is a primary concern for microprocessor designers. A very effective approach to improving the energy efficiency of a chip is to lower its supply voltage to very ...
Timothy N. Miller, Renji Thomas, James Dinan, Bruc...
ASPDAC
2010
ACM
152views Hardware» more  ASPDAC 2010»
8 years 11 months ago
Slack redistribution for graceful degradation under voltage overscaling
Modern digital IC designs have a critical operating point, or "wall of slack", that limits voltage scaling. Even with an errortolerance mechanism, scaling voltage below a...
Andrew B. Kahng, Seokhyeong Kang, Rakesh Kumar, Jo...
VLSI
2010
Springer
8 years 11 months ago
Fine-grained post placement voltage assignment considering level shifter overhead
—Multi-Vdd techniques enable application of lower supply voltage levels on cells with timing slacks. New voltage assignment, placement and voltage island partitioning methods are...
Zohreh Karimi, Majid Sarrafzadeh
ISQED
2010
IEEE
127views Hardware» more  ISQED 2010»
8 years 12 months ago
Limits of bias based assist methods in nano-scale 6T SRAM
Reduced device dimensions and operating voltages that accompany technology scaling have led to increased design challenges with each successive technology node. Large scale 6T SRA...
Randy W. Mann, Satyanand Nalam, Jiajing Wang, Bent...
TVLSI
2002
107views more  TVLSI 2002»
9 years 1 months ago
Low-power clock distribution using multiple voltages and reduced swings
: Clock networks account for a significant fraction of the power dissipation of a chip and are critical to performance. This paper presents theory and algorithms for building a low...
Jatuchai Pangjun, Sachin S. Sapatnekar
JCSC
2002
129views more  JCSC 2002»
9 years 1 months ago
Leakage Current Reduction in VLSI Systems
There is a growing need to analyze and optimize the stand-by component of power in digital circuits designed for portable and battery-powered applications. Since these circuits re...
David Blaauw, Steven M. Martin, Trevor N. Mudge, K...
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