Sciweavers

RTSS
2005
IEEE
13 years 10 months ago
Energy-Aware Modeling and Scheduling of Real-Time Tasks for Dynamic Voltage Scaling
Abstract— Dynamic voltage scaling (DVS) is a promising technique for battery-powered systems to conserve energy consumption. Most existing DVS algorithms assume information about...
Xiliang Zhong, Cheng-Zhong Xu
ISQED
2005
IEEE
108views Hardware» more  ISQED 2005»
13 years 10 months ago
Error Analysis for the Support of Robust Voltage Scaling
Recently, a new Dynamic Voltage Scaling (DVS) scheme has been proposed that increases energy efficiency significantly by allowing the processor to operate at or slightly below the...
David Roberts, Todd M. Austin, David Blaauw, Trevo...
DATE
2005
IEEE
96views Hardware» more  DATE 2005»
13 years 10 months ago
DVS for On-Chip Bus Designs Based on Timing Error Correction
On-chip buses are typically designed to meet performance constraints at worst-case conditions, including process corner, temperature, IR-drop, and neighboring net switching patter...
Himanshu Kaul, Dennis Sylvester, David Blaauw, Tre...
DATE
2005
IEEE
120views Hardware» more  DATE 2005»
13 years 10 months ago
Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints
Supply voltage scaling and adaptive body-biasing are important techniques that help to reduce the energy dissipation of embedded systems. This is achieved by dynamically adjusting...
Alexandru Andrei, Marcus T. Schmitz, Petru Eles, Z...
ISPD
2006
ACM
84views Hardware» more  ISPD 2006»
13 years 10 months ago
Integrated retiming and simultaneous Vdd/Vth scaling for total power minimization
The integration of retiming and simultaneous supply/threshold voltage scaling has a potential to enable more rigorous total power reduction. However, such integration is a highly ...
Mongkol Ekpanyapong, Sung Kyu Lim
HIPEAC
2007
Springer
13 years 10 months ago
Leveraging High Performance Data Cache Techniques to Save Power in Embedded Systems
Voltage scaling reduces leakage power for cache lines unlikely to be referenced soon. Partitioning reduces dynamic power via smaller, specialized structures. We combine approaches,...
Major Bhadauria, Sally A. McKee, Karan Singh, Gary...
ISCAS
2007
IEEE
97views Hardware» more  ISCAS 2007»
13 years 10 months ago
Comparative Analysis of Ultra-Low Voltage Flip-Flops for Energy Efficiency
—The wide use of voltage scaling along with pipelining makes flip-flops particularly important at ultra-low voltages. In this paper, the impact of voltage scaling on the performa...
Bo Fu, Paul Ampadu
DATE
2007
IEEE
156views Hardware» more  DATE 2007»
13 years 10 months ago
Process variation tolerant low power DCT architecture
: 2-D Discrete Cosine Transform (DCT) is widely used as the core of digital image and video compression. In this paper, we present a novel DCT architecture that allows aggressive v...
Nilanjan Banerjee, Georgios Karakonstantis, Kaushi...
ASPDAC
2009
ACM
115views Hardware» more  ASPDAC 2009»
13 years 11 months ago
Scheduled voltage scaling for increasing lifetime in the presence of NBTI
— Negative Bias Temperature Instability (NBTI) is a leading reliability concern for integrated circuits (ICs). It gradually increases the threshold voltages of PMOS transistors, ...
Lide Zhang, Robert P. Dick
MICRO
2009
IEEE
178views Hardware» more  MICRO 2009»
13 years 11 months ago
Improving cache lifetime reliability at ultra-low voltages
Voltage scaling is one of the most effective mechanisms to reduce microprocessor power consumption. However, the increased severity of manufacturing-induced parameter variations a...
Zeshan Chishti, Alaa R. Alameldeen, Chris Wilkerso...