Sciweavers

VTS
1995
IEEE
100views Hardware» more  VTS 1995»
13 years 7 months ago
Transformed pseudo-random patterns for BIST
This paper presents a new approach for on-chip test pattern generation. The set of test patterns generated by a pseudo-random pattern generator (e.g., an LFSR) is transformed into...
Nur A. Touba, Edward J. McCluskey
VTS
1995
IEEE
99views Hardware» more  VTS 1995»
13 years 7 months ago
Arithmetic built-in self test for high-level synthesis
In this paper, we propose an entirely new Built-In Self Test scheme for high-level synthesis of data path architectures that makes use of the arithmetic blocks in the data path to...
Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerz...
VTS
1995
IEEE
94views Hardware» more  VTS 1995»
13 years 7 months ago
Synthesis of locally exhaustive test pattern generators
Optimized locally exhaustive test pattern generators based on linear sums promise a low overhead, but have an irregular structure. The paper presents a new algorithm able to compu...
Günter Kemnitz
VTS
1995
IEEE
105views Hardware» more  VTS 1995»
13 years 7 months ago
Cyclic stress tests for full scan circuits
To ensure the production of reliable circuits and fully testable unpackaged dies for MCMs burn-in, both dynamic and monitored, remains a feasible option. During this burn-in proce...
Vinay Dabholkar, Sreejit Chakravarty, J. Najm, Jan...
VTS
1995
IEEE
114views Hardware» more  VTS 1995»
13 years 7 months ago
A portable ATPG tool for parallel and distributed systems
Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo,...
VTS
1995
IEEE
80views Hardware» more  VTS 1995»
13 years 7 months ago
Improving topological ATPG with symbolic techniques
Fulvio Corno, Paolo Prinetto, Matteo Sonza Reorda,...
VTS
1995
IEEE
76views Hardware» more  VTS 1995»
13 years 7 months ago
Reliability evaluation of combinational logic circuits by symbolic simulation
Alessandro Bogliolo, Maurizio Damiani, Piero Olivo...