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VTS
2005
IEEE
95views Hardware» more  VTS 2005»
11 years 7 months ago
SRAM Retention Testing: Zero Incremental Time Integration with March Algorithms
Testing data retention faults (DRFs), particularly in integrated systems on chip comprised of very large number of various sizes and types of embedded SRAMs is challenging and typ...
Baosheng Wang, Yuejian Wu, Josh Yang, André...
VTS
2005
IEEE
97views Hardware» more  VTS 2005»
11 years 7 months ago
Static Compaction of Delay Tests Considering Power Supply Noise
Excessive power supply noise can lead to overkill during delay test. A static compaction algorithm is described in this paper that prevents such overkill. A power supply noise est...
Jing Wang 0006, Xiang Lu, Wangqi Qiu, Ziding Yue, ...
VTS
2005
IEEE
151views Hardware» more  VTS 2005»
11 years 7 months ago
A CMOS RF RMS Detector for Built-in Testing of Wireless Transceivers
: This project involves the design of a CMOS RF RMS Detector that converts the RMS voltage amplitude of an RF signal to a DC voltage. Its high input impedance and small area make i...
Alberto Valdes-Garcia, Radhika Venkatasubramanian,...
VTS
2005
IEEE
116views Hardware» more  VTS 2005»
11 years 7 months ago
Closed-Form Simulation and Robustness Models for SEU-Tolerant Design
— A closed-form model for simulation and analysis of voltage transients caused by single-event upsets (SEUs) in logic circuits is described. A linear RC model, derived using a SP...
Kartik Mohanram
VTS
2005
IEEE
84views Hardware» more  VTS 2005»
11 years 7 months ago
Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies
We present three resistive bridging fault models valid for different CMOS technologies. The models are partitioned into a general framework (which is shared by all three models) a...
Ilia Polian, Sandip Kundu, Jean Marc Galliè...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
11 years 7 months ago
Effective TARO Pattern Generation
TARO test patterns are transition fault test patterns that sensitize each transition fault to all of the outputs that can be reached from the fault location. We were not able to i...
Intaik Park, Ahmad A. Al-Yamani, Edward J. McClusk...
VTS
2005
IEEE
96views Hardware» more  VTS 2005»
11 years 7 months ago
Pseudo-Functional Scan-based BIST for Delay Fault
This paper presents a pseudo-functional BIST scheme that attempts to minimize the over-testing problem of logic BIST for delay and crosstalk-induced failures. The over-testing pro...
Yung-Chieh Lin, Feng Lu, Kwang-Ting Cheng
VTS
2005
IEEE
101views Hardware» more  VTS 2005»
11 years 7 months ago
On-Chip Spectrum Analyzer for Analog Built-In Self Test
This paper presents the design of an on-chip spectrum analyzer. A novel architecture is used to mitigate the problems encountered in trying to implement architectures employed in ...
Anup P. Jose, Keith A. Jenkins, Scott K. Reynolds
VTS
2005
IEEE
102views Hardware» more  VTS 2005»
11 years 7 months ago
An Efficient Random Jitter Measurement Technique Using Fast Comparator Sampling
This paper describes a random jitter measurement technique using simple algorithms and comparator sampling. The approach facilitates using Automated Test Equipment (ATE) to valida...
Dongwoo Hong, Cameron Dryden, Gordon Saksena
VTS
2005
IEEE
162views Hardware» more  VTS 2005»
11 years 7 months ago
Low-Cost Alternate EVM Test for Wireless Receiver Systems
† In digital radio applications, error-vector-magnitude (EVM) is the primary specification which quantifies the performance of digital modulation implemented in silicon. Producti...
Achintya Halder, Abhijit Chatterjee
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