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DATE
2005
IEEE
99views Hardware» more  DATE 2005»
13 years 10 months ago
A New System Design Methodology for Wire Pipelined SoC
Wire Pipelining (WP) has been proposed in order to limit the impact of increasing wire delays. In general, the added pipeline elements alters the system such that architectural ch...
Mario R. Casu, Luca Macchiarulo
ICCAD
2004
IEEE
87views Hardware» more  ICCAD 2004»
14 years 1 months ago
Exploiting level sensitive latches in wire pipelining
Wire pipelining emerges as a new necessity for global wires due to increasing wire delay, shrinking clock period and growing chip size. Existing approaches on wire pipelining are ...
V. Seth, Min Zhao, Jiang Hu
DAC
2004
ACM
14 years 5 months ago
A method for correcting the functionality of a wire-pipelined circuit
As across-chip interconnect delays can exceed a clock cycle, wire pipelining becomes essential in high performance designs. Although it allows higher clock frequencies, it may cha...
Vidyasagar Nookala, Sachin S. Sapatnekar