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184views
16 years 10 months ago
Design and Evaluation of Feedback Consolidation for ABR Point-to-Multipoint Connections in ATM Networks
The available bit rate (ABR) service is proposed to transport data traffic in asynchronous transfer mode (ATM) networks. ABR is unique because the network switches can indicate to ...
Sonia Fahmy, Raj Jain, Rohit Goyal, Bobby Vandalor...
127
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AAAIDEA
2005
IEEE
15 years 5 months ago
Design and Evaluation of Diffserv Functionalities in the MPLS Edge Router Architecture
—Differentiated Service (DiffServ) in combination with Multi-Protocol Label Switching (MPLS) is a promising technology in converting the best-effort Internet into a QoS-capable n...
Wei-Chu Lai, Kuo-Ching Wu, Ting-Chao Hou
FPL
2000
Springer
119views Hardware» more  FPL 2000»
15 years 3 months ago
A Self-Reconfigurable Gate Array Architecture
Abstract. This paper presents an innovative architecture for a reconfigurable device that allows single cycle context switching and single cycle random access to the unified on-chi...
Reetinder P. S. Sidhu, Sameer Wadhwa, Alessandro M...
103
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SDL
2003
147views Hardware» more  SDL 2003»
15 years 1 months ago
Modelling and Evaluation of a Network on Chip Architecture Using SDL
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. ...
Rickard Holsmark, Magnus Högberg, Shashi Kuma...
119
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HPCA
2006
IEEE
16 years 1 days ago
BulletProof: a defect-tolerant CMP switch architecture
As silicon technologies move into the nanometer regime, transistor reliability is expected to wane as devices become subject to extreme process variation, particle-induced transie...
Kypros Constantinides, Stephen Plaza, Jason A. Blo...