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» A Network on Chip Architecture and Design Methodology
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DATE
2003
IEEE
108views Hardware» more  DATE 2003»
15 years 5 months ago
System-Level Power Analysis Methodology Applied to the AMBA AHB Bus
The specification on power consumption of a digital system is extremely important due to the growing relevance of the market of portable devices and must be taken into account sin...
Marco Caldari, Massimo Conti, Massimo Coppola, Pao...
CAL
2006
14 years 11 months ago
An Efficient, Practical Parallelization Methodology for Multicore Architecture Simulation
Multiple core designs have become commonplace in the processor market, and are hence a major focus in modern computer architecture research. Thus, for both product development and ...
James Donald, Margaret Martonosi
ICETET
2009
IEEE
15 years 6 months ago
Low Energy Tree Based Network on Chip Architectures Using Homogeneous Routers for Bandwidth and Latency Constrained Multimedia A
Abstract— Design of Network on chip architectures for multimedia applications is being widely studied. This involves design decisions at various levels of hierarchy. Topology des...
Deepak Majeti, Aditya Pasalapudi, Kishore Yalamanc...
DAC
2002
ACM
16 years 20 days ago
The next chip challenge: effective methods for viable mixed technology SoCs
The next generation of computer chips will continue the trend for more complexity than their predecessors. Many of them will contain different chip technologies and are termed SoC...
H. Bernhard Pogge
DAC
2001
ACM
16 years 20 days ago
Automatic Generation of Application-Specific Architectures for Heterogeneous Multiprocessor System-on-Chip
We present a design flow for the generation of application-specific multiprocessor architectures. In the flow, architectural parameters are first extracted from a high-level syste...
Damien Lyonnard, Sungjoo Yoo, Amer Baghdadi, Ahmed...