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» A Network on Chip Architecture and Design Methodology
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CODES
2009
IEEE
15 years 6 months ago
An on-chip interconnect and protocol stack for multiple communication paradigms and programming models
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
Andreas Hansson, Kees Goossens
DAC
2006
ACM
15 years 5 months ago
Visibility enhancement for silicon debug
Several emerging Design-for-Debug (DFD) methodologies are addressing silicon debug by making internal signal values and other data observable. Most of these methodologies require ...
Yu-Chin Hsu, Fur-Shing Tsai, Wells Jong, Ying-Tsai...
DSD
2006
IEEE
159views Hardware» more  DSD 2006»
15 years 5 months ago
Deadlock Free Routing Algorithms for Mesh Topology NoC Systems with Regions
Region concept helps to accommodate cores larger than the tile size in mesh topology NoC architectures. In addition, it offers many new opportunities for NoC design, as well as pr...
Rickard Holsmark, Maurizio Palesi, Shashi Kumar
LPNMR
2009
Springer
15 years 6 months ago
Application of ASP for Automatic Synthesis of Flexible Multiprocessor Systems from Parallel Programs
Configurable on chip multiprocessor systems combine advantages of task-level parallelism and the flexibility of field-programmable devices to customize architectures for paralle...
Harold Ishebabi, Philipp Mahr, Christophe Bobda, M...
IMC
2007
ACM
15 years 1 months ago
Measuring load-balanced paths in the internet
Tools to measure internet properties usually assume the existence of just one single path from a source to a destination. However, load-balancing capabilities, which create multip...
Brice Augustin, Timur Friedman, Renata Teixeira