Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
Wireless IEEE 802.11 networks in residences, small businesses, and public “hot spots” typically encounter the wireline access link (DSL, cable modem, T1, etc.) as the slowest ...
Violeta Gambiroza, Bahareh Sadeghi, Edward W. Knig...
Existing work on the capacity of wireless networks predominantly considers homogeneous random networks with random work load. The most relevant bounds on the network capacity, e.g...
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...