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» A Network on Chip Architecture and Design Methodology
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ISQED
2008
IEEE
153views Hardware» more  ISQED 2008»
15 years 6 months ago
Accelerating Clock Mesh Simulation Using Matrix-Level Macromodels and Dynamic Time Step Rounding
Clock meshes have found increasingly wide applications in today’s high-performance IC designs. The inherent routing redundancies associated with clock meshes lead to improved cl...
Xiaoji Ye, Min Zhao, Rajendran Panda, Peng Li, Jia...
DAC
2008
ACM
16 years 20 days ago
Variation-adaptive feedback control for networks-on-chip with multiple clock domains
This paper discusses the use of networks-on-chip (NoCs) consisting of multiple voltage-frequency islands to cope with power consumption, clock distribution and parameter variation...
Ümit Y. Ogras, Diana Marculescu, Radu Marcule...
MOBICOM
2004
ACM
15 years 5 months ago
End-to-end performance and fairness in multihop wireless backhaul networks
Wireless IEEE 802.11 networks in residences, small businesses, and public “hot spots” typically encounter the wireline access link (DSL, cable modem, T1, etc.) as the slowest ...
Violeta Gambiroza, Bahareh Sadeghi, Edward W. Knig...
MOBIHOC
2007
ACM
15 years 11 months ago
Bounds for the capacity of wireless multihop networks imposed by topology and demand
Existing work on the capacity of wireless networks predominantly considers homogeneous random networks with random work load. The most relevant bounds on the network capacity, e.g...
Alireza Keshavarz-Haddad, Rudolf H. Riedi
CASES
2008
ACM
15 years 1 months ago
StageNetSlice: a reconfigurable microarchitecture building block for resilient CMP systems
Although CMOS feature size scaling has been the source of dramatic performance gains, it has lead to mounting reliability concerns due to increasing power densities and on-chip te...
Shantanu Gupta, Shuguang Feng, Amin Ansari, Jason ...