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IPPS
2007
IEEE
15 years 6 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...
DIAGRAMS
2004
Springer
15 years 5 months ago
Cider: A Component-Based Toolkit for Creating Smart Diagram Environments
— Smart Diagram Environments (SDEs) are software applications that use structured diagrams to provide a natural visual interface that behaves as if the computer “understands”...
Anthony R. Jansen, Kim Marriott, Bernd Meyer
ISCAS
2003
IEEE
129views Hardware» more  ISCAS 2003»
15 years 5 months ago
SONICmole: a debugging environment for the UltraSONIC reconfigurable computer
Reconfigurable Computers based on a combination of conventional microprocessors and Field Programmable Gate Arrays (FPGAs) presents new challenges to designers. Debugging on such ...
Theerayod Wiangtong, Chun Te Ewe, Peter Y. K. Cheu...
WORDS
2003
IEEE
15 years 5 months ago
Timing Analysis of Optimised Code
Timing analysis is a crucial test for dependable hard real-time systems (DHRTS). The calculation of the worst-case execution time (WCET) is mandatory. As modern compilers are capa...
Raimund Kirner, Peter P. Puschner
CC
2003
Springer
192views System Software» more  CC 2003»
15 years 5 months ago
Address Register Assignment for Reducing Code Size
Abstract. In DSP processors, minimizing the amount of address calculations is critical for reducing code size and improving performance since studies of programs have shown that in...
Mahmut T. Kandemir, Mary Jane Irwin, Guilin Chen, ...