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ICCD
1993
IEEE
111views Hardware» more  ICCD 1993»
15 years 10 months ago
Ravel-XL: A Hardware Accelerator for Assigned-Delay Compiled-Code Logic Gate Simulation
Ravel-XL is a single-boardhardware accelerator for gate-level digital logic simulation. It uses a standard levelizedcode approach to statically schedule gate evaluations.However, u...
Michael A. Riepe, João P. Marques Silva, Ka...
167
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ASPDAC
2007
ACM
132views Hardware» more  ASPDAC 2007»
15 years 10 months ago
Fast Decoupling Capacitor Budgeting for Power/Ground Network Using Random Walk Approach
- This paper proposes a fast and practical decoupling capacitor (decap) budgeting algorithm to optimize the power ground (P/G) network design. The new method adopts a modified rand...
Le Kang, Yici Cai, Yi Zou, Jin Shi, Xianlong Hong,...
CIA
2006
Springer
15 years 9 months ago
Iterative Query-Based Approach to Efficient Task Decomposition and Resource Allocation
Intelligent coordination in complex multi-agent environments requires sophisticated mechanisms for suboptimal task decomposition and efficient resource allocation provided by the t...
Michal Pechoucek, Ondrej Lerch, Jirí B&iacu...
CIT
2006
Springer
15 years 9 months ago
Bridging the Gap Between Reality and Simulations: An Ethernet Case Study
Simulation is a widely used technique in networking research and a practice that has suffered loss of credibility in recent years due to doubts about its reliability. In this pape...
Punit Rathod, Srinath Perur, Raghuraman Rangarajan
ICCD
1991
IEEE
65views Hardware» more  ICCD 1991»
15 years 9 months ago
Self-Timed Logic Using Current-Sensing Completion Detection (CSCD)
This article proposes a completion-detection method for efficiently implementing Boolean functions as self-timed logic structures. Current-Sensing Completion Detection, CSCD, allow...
Mark E. Dean, David L. Dill, Mark Horowitz