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» An interconnection architecture for micropayment systems
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DAC
2010
ACM
15 years 3 months ago
Cost-driven 3D integration with interconnect layers
The ever increasing die area of Chip Multiprocessors (CMPs) affects manufacturing yield, resulting in higher manufacture cost. Meanwhile, network-on-chip (NoC) has emerged as a p...
Xiaoxia Wu, Guangyu Sun, Xiangyu Dong, Reetuparna ...
89
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IPPS
2006
IEEE
15 years 5 months ago
Performance evaluation of wormhole routed network processor-memory interconnects
Network line cards are experiencing ever increasing line rates, random data bursts, and limited space. Hence, they are more vulnerable than other processormemory environments, to ...
Taskin Koçak, Jacob Engel
FTDCS
1999
IEEE
15 years 4 months ago
Internet - Intranet - Infranet: A Modular Integrating Architecture
Based on an analysis of the heterogeneous systems for interconnecting distributed infrastructural devices, such as low-bandwidth sensor/actuator-networks and upcoming multimedia h...
Tom Pfeifer
ISCAS
2005
IEEE
113views Hardware» more  ISCAS 2005»
15 years 5 months ago
Effect of traffic localization on energy dissipation in NoC-based interconnect
Multiprocessor system-on-chip (MP-SoC) platforms are emerging as an important trend of SoC design. Scaleable communication-centric interconnect fabrics such as networks-onchip (No...
Partha Pratim Pande, Cristian Grecu, Michael Jones...
HPCA
2003
IEEE
16 years 1 days ago
A Methodology for Designing Efficient On-Chip Interconnects on Well-Behaved Communication Patterns
As the level of chip integration continues to advance at a fast pace, the desire for efficient interconnects-whether on-chip or off-chip--is rapidly increasing. Traditional interc...
Wai Hong Ho, Timothy Mark Pinkston