443 search results - page 17 / 89 » An interconnection architecture for micropayment systems |
WIESS
2000
15 years 1 months ago
2000
The HP V-Class server family provides up to 32 processors and 32 GB of memory in a single cabinet. Scalable Computing Architecture technology allows multiple V-Class cabinets to b...
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MICRO
2009
IEEE
15 years 6 months ago
2009
IEEE
Modern DRAM systems rely on memory controllers that employ out-of-order scheduling to maximize row access locality and bank-level parallelism, which in turn maximizes DRAM bandwid...
CSMR
2008
IEEE
15 years 6 months ago
2008
IEEE
Modern software systems are highly interconnected and have been under constant change for many years. IT decision makers find it difficult to predict and plan change projects due ...
CODES
2004
IEEE
15 years 3 months ago
2004
IEEE
In this paper, we present an approach for automatic synthesis of System on Chip (SoC) multiprocessor architectures for applications expressed as process networks. Our approach is ...
DAC
1996
ACM
15 years 3 months ago
1996
ACM
This paper presents a new concept for accurate modeling and timing simulationof electronicsystems integrated in a typical VHDL design environment, taking into account the requirem...