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» An interconnection architecture for micropayment systems
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DAC
1999
ACM
15 years 4 months ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
ISQED
2006
IEEE
90views Hardware» more  ISQED 2006»
15 years 5 months ago
Transaction Level Error Susceptibility Model for Bus Based SoC Architectures
System on Chip architectures have traditionally relied upon bus based interconnect for their communication needs. However, increasing bus frequencies and the load on the bus calls...
Ing-Chao Lin, Suresh Srinivasan, Narayanan Vijaykr...
HPCA
2003
IEEE
16 years 1 days ago
Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks
Originally developed to connect processors and memories in multicomputers, prior research and design of interconnection networks have focused largely on performance. As these netw...
Li Shang, Li-Shiuan Peh, Niraj K. Jha
SLIP
2009
ACM
15 years 6 months ago
Honeycomb-structured computational interconnects and their scalable extension to spherical domains
The present paper is part of a larger effort to redesign, from the ground up, the best possible interconnect topologies for switchless multiprocessor computer systems. We focus he...
Joseph B. Cessna, Thomas R. Bewley
DAC
2006
ACM
16 years 20 days ago
GreenBus: a generic interconnect fabric for transaction level modelling
In this paper we present a generic interconnect fabric for transaction level modelling tackeling three major aspects. First, a review of the bus and IO structures that we have ana...
Wolfgang Klingauf, Robert Günzel, Oliver Brin...