443 search results - page 21 / 89 » An interconnection architecture for micropayment systems |
115
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HPCA
2009
IEEE
16 years 7 days ago
2009
IEEE
Performance and power consumption of an on-chip interconnect that forms the backbone of Chip Multiprocessors (CMPs), are directly influenced by the underlying network topology. Bo...
HPCA
2009
IEEE
15 years 6 months ago
2009
IEEE
On-network hardware support for multi-destination traffic is a desirable feature in most multiprocessor machines. Multicast hardware capabilities enable much more effective bandwi...
114
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NOCS
2007
IEEE
15 years 6 months ago
2007
IEEE
Abstract— The behaviour of systems on chip (SOC) is complex because they contain multiple processors that interact through concurrent interconnects, such as networks on chip (NOC...
114
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CODES
2009
IEEE
15 years 6 months ago
2009
IEEE
A growing number of applications, with diverse requirements, are integrated on the same System on Chip (SoC) in the form of hardware and software Intellectual Property (IP). The d...
ISCA
2007
IEEE
15 years 6 months ago
2007
IEEE
Due to wire delay scalability and bandwidth limitations inherent in shared buses and dedicated links, packet-switched on-chip interconnection networks are fast emerging as the per...