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DATE
2007
IEEE
107views Hardware» more  DATE 2007»
15 years 6 months ago
Routing table minimization for irregular mesh NoCs
The majority of current Network on Chip (NoC) architectures employ mesh topology and use simple static routing, to reduce power and area. However, regular mesh topology is unreali...
Evgeny Bolotin, Israel Cidon, Ran Ginosar, Avinoam...
ICCAD
2005
IEEE
147views Hardware» more  ICCAD 2005»
15 years 8 months ago
NoCEE: energy macro-model extraction methodology for network on chip routers
In this paper we present NoCEE, a fast and accurate method for extracting energy models for packet-switched Network on Chip (NoC) routers. Linear regression is used to model the r...
Jeremy Chan, Sri Parameswaran
CODES
2007
IEEE
15 years 6 months ago
Channel trees: reducing latency by sharing time slots in time-multiplexed networks on chip
Networks on Chip (NoC) have emerged as the design paradigm for scalable System on Chip communication infrastructure. A growing number of applications, often with firm (FRT) or so...
Andreas Hansson, Martijn Coenen, Kees Goossens
ISCAS
2005
IEEE
154views Hardware» more  ISCAS 2005»
15 years 5 months ago
HIBI-based multiprocessor SoC on FPGA
Abstract — FPGAs offer excellent platform for System-onChips consisting of Intellectual Property (IP) blocks. The problem is that IP blocks and their interconnections are often F...
Erno Salminen, Ari Kulmala, Timo D. Hämä...
JSA
2007
162views more  JSA 2007»
14 years 11 months ago
Exploration of distributed shared memory architectures for NoC-based multiprocessors
Multiprocessor system-on-chip (MP-SoC) platforms represent an emerging trend for embedded multimedia applications. To enable MP-SoC platforms, scalable communication-centric inter...
Matteo Monchiero, Gianluca Palermo, Cristina Silva...