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VTS
2005
IEEE
15 years 5 months ago
2005
IEEE
An automated design procedure is described for synthesizing circuits with low power concurrent error detection. It is based on pre-synthesis selection of a parity-check code follo...
ISVLSI
2002
IEEE
15 years 4 months ago
2002
IEEE
The clock distribution and generation circuitry is known to consume more than a quarter of the power budget of existing microprocessors. A previously derived clock energy model is...
IPPS
2000
IEEE
15 years 4 months ago
2000
IEEE
The work described here introduces a practical and accurate tool for predicting power consumption for FPGA circuits. The utility of the tool is that it enables FPGA circuit designe...
DAC
2001
ACM
16 years 23 days ago
2001
ACM
In modern embedded systems including communication and multimedia applications, large fraction of power is consumed during memory access and data transfer. Thus, buses should be d...
ICCAD
2003
IEEE
15 years 8 months ago
2003
IEEE
In this paper, we study the full-chp interconnect power modeling. ,We show that repeater,insertion is no longer sufficient to achievethe targetfrequencies specifiedhy ITRS, and de...