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ASAP
2007
IEEE
144views Hardware» more  ASAP 2007»
15 years 12 months ago
A High-Throughput Programmable Decoder for LDPC Convolutional Codes
In this paper, we present and analyze a novel decoder architecture for LDPC convolutional codes (LDPCCCs). The proposed architecture enables high throughput and can be programmed ...
Marcel Bimberg, Marcos B. S. Tavares, Emil Mat&uac...
IPPS
2007
IEEE
15 years 11 months ago
A Study of Design Efficiency with a High-Level Language for FPGAs
Over the years reconfigurable computing devices such as FPGAs have evolved from gate-level glue logic to complex reprogrammable processing architectures. However, the tools used f...
Zain-ul-Abdin, Bertil Svensson
ECBS
2008
IEEE
124views Hardware» more  ECBS 2008»
15 years 7 months ago
Hierarchical Model to Develop Component-Based Systems
Large and complex software systems require expressive notations for representing their software architecture. In this context Architecture Description Languages (ADLs) can be used...
Abdelkrim Amirat, Mourad Oussalah
DSS
2007
112views more  DSS 2007»
15 years 5 months ago
Service-based P2P overlay network for collaborative problem solving
This paper describes a service-based P2P overlay network architecture to support a collaborative environment for solving complex business processes over the network. In the propos...
Sanjay Goel, Shashishekara S. Talya, Michael W. So...
TC
2002
15 years 5 months ago
Finite Field Multiplier Using Redundant Representation
This article presents simple and highly regular architectures for finite field multipliers using a redundant representation. The basic idea is to embed a finite field into a cyclo...
Huapeng Wu, M. Anwarul Hasan, Ian F. Blake, Shuhon...