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DAC
2004
ACM
16 years 22 days ago
Worst-case circuit delay taking into account power supply variations
Current Static Timing Analysis (STA) techniques allow one to verify the timing of a circuit at different process corners which only consider cases where all the supplies are low o...
Dionysios Kouroussis, Rubil Ahmadi, Farid N. Najm
CF
2007
ACM
15 years 3 months ago
Automated generation of layout and control for quantum circuits
We present a computer-aided design flow for quantum circuits, complete with automatic layout and control logic extraction. To motivate automated layout for quantum circuits, we in...
Mark Whitney, Nemanja Isailovic, Yatish Patel, Joh...
GLVLSI
2005
IEEE
97views VLSI» more  GLVLSI 2005»
15 years 5 months ago
On equivalence checking and logic synthesis of circuits with a common specification
In this paper we develop a theory of equivalence checking (EC) and logic synthesis of circuits with a common specification (CS). We show that two combinational circuits N1, N2 have...
Eugene Goldberg
DAC
2006
ACM
16 years 22 days ago
State encoding of large asynchronous controllers
A novel method to solve the state encoding problem in Signal Transition Graphs is presented. It is based on the structural theory of Petri nets and can be applied to large specifi...
Josep Carmona, Jordi Cortadella
DAC
2005
ACM
15 years 1 months ago
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
In this paper, we analyze the effect of jitter in track and hold circuits. The output spectrum is obtained in terms of the system function of the track and hold. It is a fairly g...
V. Vasudevan